Estimation of remaining life using embedded SRAM for wearout parameter extraction
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[1] W. Kent Fuchs,et al. Efficient Spare Allocation in Reconfigurable Arrays , 1986, 23rd ACM/IEEE Design Automation Conference.
[2] Hiroshi Nakajima,et al. A Wearable Healthcare System With a 13.7 $\mu$ A Noise Tolerant ECG Processor , 2015, IEEE Transactions on Biomedical Circuits and Systems.
[3] Chang-Chih Chen,et al. System-level modeling of microprocessor reliability degradation due to BTI and HCI , 2014, 2014 IEEE International Reliability Physics Symposium.
[4] Shyue-Kung Lu,et al. Efficient BISR Techniques for Embedded Memories Considering Cluster Faults , 2010, 13th Pacific Rim International Symposium on Dependable Computing (PRDC 2007).
[5] Chang-Chih Chen,et al. A comparative study of wearout mechanisms in state-of-art microprocessors , 2012, 2012 IEEE 30th International Conference on Computer Design (ICCD).
[6] Tag Gon Kim,et al. An low-power microcontroller with accuracy-controlled signal-to-event converter for rare-event human activity-sensing applications , 2014, 2014 IEEE International Conference on Consumer Electronics - Taiwan.
[7] Chang-Chih Chen,et al. Impact of NBTI/PBTIon SRAMs within microprocessor systems: Modeling, simulation, and analysis , 2013, Microelectron. Reliab..
[8] Linda S. Milor,et al. Reliable cache design with on-chip monitoring of NBTI degradation in SRAM cells using BIST , 2010, 2010 28th VLSI Test Symposium (VTS).
[9] Chang-Chih Chen,et al. System-level estimation of threshold voltage degradation due to NBTI with I/O measurements , 2014, 2014 IEEE International Reliability Physics Symposium.
[10] Jeonghun Cho,et al. Accuracy-Energy Configurable Sensor Processor and IoT Device for Long-Term Activity Monitoring in Rare-Event Sensing Applications , 2014, TheScientificWorldJournal.
[11] Soonyoung Cha,et al. Memory BIST for on-chip monitoring of resistive-open defects due to electromigration and stress-induced voiding in an SRAM array , 2014, Design of Circuits and Integrated Systems.
[12] Chang-Chih Chen,et al. Diagnosis of resistive-open defects due to electromigration and stress-induced voiding in an SRAM array , 2014, 2014 IEEE International Integrated Reliability Workshop Final Report (IIRW).
[13] Robert Kwasnick,et al. Determination of CPU use conditions , 2011, 2011 International Reliability Physics Symposium.
[14] Chang-Chih Chen,et al. MBIST and statistical hypothesis test for time dependent dielectric breakdowns due to GOBD vs. BTDDB in an SRAM array , 2015, 2015 IEEE 33rd VLSI Test Symposium (VTS).
[15] Chang-Chih Chen,et al. Extraction of threshold voltage degradation modeling due to Negative Bias Temperature Instability in circuits with I/O measurements , 2014, 2014 IEEE 32nd VLSI Test Symposium (VTS).
[16] Linda Milor,et al. NBTI resistant SRAM design , 2011, 2011 4th IEEE International Workshop on Advances in Sensors and Interfaces (IWASI).
[17] Chang-Chih Chen,et al. System-level modeling and microprocessor reliability analysis for backend wearout mechanisms , 2013, 2013 Design, Automation & Test in Europe Conference & Exhibition (DATE).
[18] Chang-Chih Chen,et al. Microprocessor Aging Analysis and Reliability Modeling Due to Back-End Wearout Mechanisms , 2015, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.
[19] Jin-Fu Li,et al. Built-in redundancy analysis for memory yield improvement , 2003, IEEE Trans. Reliab..
[20] Hideto Hidaka,et al. A built-in self-repair analyzer (CRESTA) for embedded DRAMs , 2000, Proceedings International Test Conference 2000 (IEEE Cat. No.00CH37159).
[21] Sungho Kang,et al. A Fast Built-in Redundancy Analysis for Memories With Optimal Repair Rate Using a Line-Based Search Tree , 2009, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.
[22] Shyue-Kung Lu,et al. Efficient built-in redundancy analysis for embedded memories with 2-D redundancy , 2006, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.
[23] Linda S. Milor,et al. Built-in self test methodology for diagnosis of backend wearout mechanisms in SRAM cells , 2014, 2014 IEEE 32nd VLSI Test Symposium (VTS).
[24] Hans-Joachim Wunderlich,et al. An Integrated Built-In Test and Repair Approach for Memories with 2D Redundancy , 2007, 12th IEEE European Test Symposium (ETS'07).
[25] Chang-Chih Chen,et al. System-level modeling and reliability analysis of microprocessor systems , 2013, 5th IEEE International Workshop on Advances in Sensors and Interfaces IWASI.
[26] B. Sklar,et al. The ABCs of linear block codes , 2004, IEEE Signal Processing Magazine.
[27] Chang-Chih Chen,et al. System-level modeling of microprocessor reliability degradation due to TDDB , 2014, Design of Circuits and Integrated Systems.
[28] W. Kent Fuchs,et al. Efficient Spare Allocation for Reconfigurable Arrays , 1987 .
[29] Shintaro Izumi,et al. A 14µA ECG processor with noise tolerant heart rate extractor and FeRAM for wearable healthcare systems , 2015, The 20th Asia and South Pacific Design Automation Conference.