CDF(2,2) wavelet lossy image compression on primitive FPGA (XC9572)

This paper presents a hardware implementation of CDF(2,2) wavelet image compressor. The design demonstrates that high quality circuit implementation is possible through the use of suitable data organization (partitioned approach) and algorithm-to-architecture mappings (parallelism or pipelining). The main goal is to reach a higher performance and throughput with a single primitive FPGA device namely, Xilinx's XC9572. Details of the encoder design have been discussed and the results are presented.

[1]  Paul Molitor,et al.  A pipelined architecture for partitioned DWT based lossy image compression using FPGA's , 2001, FPGA '01.

[2]  Stéphane Mallat,et al.  A Theory for Multiresolution Signal Decomposition: The Wavelet Representation , 1989, IEEE Trans. Pattern Anal. Mach. Intell..

[3]  Bryan Usevitch,et al.  A tutorial on modern lossy wavelet image compression: foundations of JPEG 2000 , 2001, IEEE Signal Process. Mag..

[4]  Hyeokho Choi,et al.  Geometric tools for image compression , 2002, Conference Record of the Thirty-Sixth Asilomar Conference on Signals, Systems and Computers, 2002..

[5]  A. Robert Calderbank,et al.  Lossless image compression using integer to integer wavelet transforms , 1997, Proceedings of International Conference on Image Processing.

[6]  Jerome M. Shapiro,et al.  Embedded image coding using zerotrees of wavelet coefficients , 1993, IEEE Trans. Signal Process..

[7]  Rui Zhang,et al.  Design of optimal quantizers for distributed source coding , 2003, Data Compression Conference, 2003. Proceedings. DCC 2003.

[8]  Justin K. Romberg,et al.  Geometric methods for wavelet-based image compression , 2003, SPIE Optics + Photonics.

[9]  I. Daubechies,et al.  Biorthogonal bases of compactly supported wavelets , 1992 .