A Novel Hardware-Accelerated Priority Queue for Real-Time Systems

This paper presents an efficient hardware architecture of priority queue, which is suitable for real-time systems due to the constant response time of the queue. The proposed architecture is based on shift registers, systolic arrays, heapsort algorithm, the Rocket Queue architecture and dual-port RAMs. This architecture, called Heap Queue, can sort items according to their sorting values and can remove the first item from the queue. The implementation of the Heap Queue architecture has throughput of one instruction per two clock cycles regardless of the actual number of items in the system and regardless of the queue capacity. The developed queue is optimized for low chip area costs, which leads to lower energy consumption too. The Heap Queue architecture has constant time complexity due to two clock-cycle response time of the instructions and therefore, the architecture is highly deterministic. The usage of the queue is recommended for applications in hard real-time systems. The architecture was verified using simplified version of UVM and applying millions of randomly generated instructions. Achieved ASIC and FPGA synthesis results are presented and compared to the synthesis results of the Systolic Array and Rocket Queue architectures. More than 86% of chip area and 92% of power consumption can be saved if Heap Queue is adopted. Advantages and disadvantages of the proposed architecture in comparison to the existing architectures are discussed.