A High-Speed and Power-Efficient Voltage Level Shifter for Dual-Supply Applications

This brief presents a fast and power-efficient voltage level-shifting circuit capable of converting extremely low levels of input voltages into high output voltage levels. The efficiency of the proposed circuit is due to the fact that not only the strength of the pull-up device is significantly reduced when the pull-down device is pulling down the output node, but the strength of the pull-down device is also increased using a low-power auxiliary circuit. Postlayout simulation results of the proposed circuit in a 0.18-<inline-formula> <tex-math notation="LaTeX">$\mu \text{m}$ </tex-math></inline-formula> technology demonstrate a total energy per transition of 157 fJ, a static power dissipation of 0.3 nW, and a propagation delay of 30 ns for input frequency of 1 MHz, low supply voltage level of <inline-formula> <tex-math notation="LaTeX">$V_{\mathrm {{DDL}}}= 0.4$ </tex-math></inline-formula> V, and high supply voltage level of <inline-formula> <tex-math notation="LaTeX">$V_{\mathrm {{DDH}}}= 1.8$ </tex-math></inline-formula> V.

[1]  Reza Lotfi,et al.  A Low-Power Subthreshold to Above-Threshold Voltage Level Shifter , 2014, IEEE Transactions on Circuits and Systems II: Express Briefs.

[2]  Ameya Bhide,et al.  A 53-nW 9.1-ENOB 1-kS/s SAR ADC in 0.13-$\mu$m CMOS for Medical Implant Devices , 2012, IEEE Journal of Solid-State Circuits.

[3]  Takashi Ishikawa,et al.  Automated low-power technique exploiting multiple supply voltages applied to a media processor , 1997, Proceedings of CICC 97 - Custom Integrated Circuits Conference.

[4]  Marco Lanuzza,et al.  Fast and Wide Range Voltage Conversion in Multisupply Voltage Designs , 2015, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[5]  A. Chandrakasan,et al.  A 180-mV subthreshold FFT processor using a minimum energy design methodology , 2005, IEEE Journal of Solid-State Circuits.

[6]  Ulrich Rückert,et al.  A Subthreshold to Above-Threshold Level Shifter Comprising a Wilson Current Mirror , 2010, IEEE Transactions on Circuits and Systems II: Express Briefs.

[7]  Stefania Perri,et al.  Exploring well configurations for voltage level converter design in 28 nm UTBB FDSOI technology , 2015, 2015 33rd IEEE International Conference on Computer Design (ICCD).

[8]  Yuan-Hua Chu,et al.  A Wide-Range Level Shifter Using a Modified Wilson Current Mirror Hybrid Buffer , 2014, IEEE Transactions on Circuits and Systems I: Regular Papers.

[9]  Nobutaka Kuroki,et al.  A Low-Power Level Shifter With Logic Error Correction for Extremely Low-Voltage Digital CMOS LSIs , 2012, IEEE Journal of Solid-State Circuits.