Dynamic time-slot allocation for QoS enabled networks on chip

MP-SoCs are expected to require complex communication architectures such as NoCs. This paper presents, to our knowledge, the first algorithm to dynamically perform routing and allocation of guaranteed communication resources on NoCs that provide QoS with TDMA techniques. We test the efficiency of our algorithm by allocating the communication channels required for an application composed of a 3D pipeline and an MPEG-2 decoder/encoder video chain on a 16 node MP-SoC. Dynamism in the communication is created by the 3D application. On a StrongARM processor clocked at 200 MHz, the allocation time for one time-slot takes about 1000 cycles per hop in the connection. We show that central time-slot allocation algorithms are practical for small-scale MP-SoC systems. Indeed, our algorithm can compute the allocation of 40 connections for a complex scene of the 3D pipeline in 450 to 900 /spl mu/s, depending on the slot table size.

[1]  Om Prakash Gangwal,et al.  Building Predictable Systems on Chip: An Analysis of Guaranteed Communication in the Aethereal Network on Chip , 2005 .

[2]  Peter Norvig,et al.  Artificial Intelligence: A Modern Approach , 1995 .

[3]  Om Prakash Gangwal,et al.  An efficient on-chip NI offering guaranteed services, shared-memory abstraction, and flexible network configuration , 2005 .

[4]  Wayne Piekarski,et al.  ARQuake: the outdoor augmented reality gaming system , 2002, CACM.

[5]  Rudy Lauwereins,et al.  Networks on Chip as Hardware Components of an OS for Reconfigurable Systems , 2003, FPL.

[6]  Rudy Lauwereins,et al.  Highly scalable network on chip for reconfigurable systems , 2003, Proceedings. 2003 International Symposium on System-on-Chip (IEEE Cat. No.03EX748).

[7]  Diederik Verkest,et al.  Operating-system controlled network on chip , 2004, Proceedings. 41st Design Automation Conference, 2004..

[8]  Axel Jantsch,et al.  Will Networks on Chip Close the Productivity Gap? , 2003, Networks on Chip.

[9]  Axel Jantsch,et al.  A network on chip architecture and design methodology , 2002, Proceedings IEEE Computer Society Annual Symposium on VLSI. New Paradigms for VLSI Systems Design. ISVLSI 2002.

[10]  Kees G. W. Goossens,et al.  An efficient on-chip network interface offering guaranteed services, shared-memory abstraction, and flexible network configuration , 2004, Proceedings Design, Automation and Test in Europe Conference and Exhibition.

[11]  Hugo De Man On Nanoscale Integration and Gigascale Complexity in the Post.Com World , 2002, DATE.