Design and Implementation of Block-Based Partitioning for Parallel Flip-Chip Power-Grid Analysis

Power-grid analysis is one of the critical design steps to ensure circuit reliability and achieve performance targets for very large scale integration systems. With each new technology generation, the circuit size has decreased and the power density has increased. Consequently, power-grid analysis has become ever more complex with greater CPU runtime and memory usage requirements. For a state-of-the-art power-grid design with more than 100-million nodes, it is often desirable to partition the power grid into smaller regions and analyze them in parallel by exploiting the locality of flip-chip packages. However, the traditional area-based partitioning strategy may not be best suited to analyze the DC current and ohmic IR voltage drop of a design that has irregular power rails and nonuniform power consumption because such nonuniformity affects the locality of power supply network and the accuracy of analysis. In this paper, we will present the analysis of a flip-chip design with 136-million nodes and propose a block-based partitioning scheme to improve the accuracy of parallel power-grid analysis.

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