NOVEL REAL-TIME FPGA-BASED QRS DETECTOR USING ADAPTIVE THRESHOLD WITH THE PREVIOUS SMALLEST PEAK OF ECG SIGNAL

The QRS complex of the ECG signal is the reference point for the most ECG applications. In this paper, we aim to describe the design and the implementation of an embedded system for detection of the QRS complexes in real-time. The design is based on the notorious algorithm of Pan & Tompkins, with a novel simple idea for the decision stage of this algorithm. The implementation uses a circuit of the current trend, i.e. the FPGA, and it is developed with the Xilinx design tool, System Generator for DSP. In the authors’ view, the specific feature, i.e. authenticity and simplicity of the proposed model, is that the threshold value is updated from the previous smallest peak; in addition, the model is entirely designed simply with MCode blocks. The hardware design is tested with five 30 minutes data records obtained from the MIT-BIH Arrhythmia database. Its accuracy exceeds 96%, knowing that four records among the five represent the worst cases in the database. In terms of the resources utilization, our implementation occupies around 30% of the used FPGA device, namely the Xilinx Spartan 3E XC3S500.