Systolic array based concurrent processing for real-time high performance control

Concurrent processing techniques are applied to real-time high-performance control problems. In particular, four shortest-latency systolic array architectures are developed for controller implementation in such problems at word level. A technique termed 'M-expanded pipelining' is used to pipeline these architectures to an arbitrary deeper level. Some preliminary results concerning the expected performance of these architectures are presented.<<ETX>>