Energy-driven integrated hardware-software optimizations using SimplePower

With the emergence of a plethora of embedded and portable applications, energy dissipation has joined throughput, area, and accuracy/precision as a major design constraint. Thus, designers must be concerned with both optimizing and estimating the energy consumption of circuits, architectures, and software. Most of the research in energy optimization and/or estimation has focused on single components of the system and has not looked across the interacting spectrum of the hardware and software. The novelty of our new energy estimation framework, SimplePower, is that it evaluates the energy considering the system as a whole rather than just as a sum of parts, and that it concurrently supports both compiler and architectural experimentation. We present the design and use of the SimplePower framework that includes a transition-sensitive, cycle-accurate datapath energy model that interfaces with analytical and transition sensitive energy models for the memory and bus subsystems, respectively. We analyzed the energy consumption of ten codes from the multidimensional array domain, a domain that is important for embedded video and signal processing systems, after applying different compiler and architectural optimizations. Our experiments demonstrate that early estimates from the SimplePower energy estimation framework can help identify the system energy hotspots and enable architects and compiler designers to focus their efforts on these areas.

[1]  Mary Jane Irwin,et al.  Energy characterization based on clustering , 1996, DAC '96.

[2]  Jörg Henkel,et al.  A framework for estimating and minimizing energy dissipation of embedded HW/SW systems , 2001 .

[3]  Todd M. Austin,et al.  The SimpleScalar tool set, version 2.0 , 1997, CARN.

[4]  Michael Wolfe,et al.  High performance compilers for parallel computing , 1995 .

[5]  Mary Jane Irwin,et al.  Energy issues in multimedia systems , 1999, 1999 IEEE Workshop on Signal Processing Systems. SiPS 99. Design and Implementation (Cat. No.99TH8461).

[6]  Chaitali Chakrabarti,et al.  Memory exploration for low power, embedded systems , 1999, DAC '99.

[7]  Dake Liu,et al.  Power consumption estimation in CMOS VLSI chips , 1994, IEEE J. Solid State Circuits.

[8]  Kanad Ghose,et al.  Analytical energy dissipation models for low-power caches , 1997, ISLPED '97.

[9]  Toru Shimizu,et al.  M32R/D-integrating DRAM and microprocessor , 1997, IEEE Micro.

[10]  R. E. Kessler,et al.  Inexpensive implementations of set-associativity , 1989, ISCA '89.

[11]  Alvin M. Despain,et al.  Cache designs for energy efficiency , 1995, Proceedings of the Twenty-Eighth Annual Hawaii International Conference on System Sciences.

[12]  Narayanan Vijaykrishnan,et al.  Clock power issues in system-on-a-chip designs , 1999, Proceedings. IEEE Computer Society Workshop on VLSI '99. System Design: Towards System-on-a-Chip Paradigm.

[13]  Steve Carr,et al.  Unroll-and-jam using uniformly generated sets , 1997, Proceedings of 30th Annual International Symposium on Microarchitecture.

[14]  William H. Mangione-Smith,et al.  The filter cache: an energy efficient memory structure , 1997, Proceedings of 30th Annual International Symposium on Microarchitecture.

[15]  Mary Jane Irwin,et al.  Validation of an architectural level power analysis technique , 1998, DAC.

[16]  Sharad Malik,et al.  Instruction level power analysis and optimization of software , 1996, J. VLSI Signal Process..

[17]  Stan Y. Liao,et al.  Code generation and optimization for embedded digital signal processors , 1996 .

[18]  Y. Nakagome,et al.  Trends in low-power RAM circuit technologies , 1995 .

[19]  Kazuaki Murakami,et al.  Way-predicting set-associative cache for high performance and low energy consumption , 1999, Proceedings. 1999 International Symposium on Low Power Electronics and Design (Cat. No.99TH8477).

[20]  Sharad Malik,et al.  Instruction level power analysis and optimization of software , 1996, Proceedings of 9th International Conference on VLSI Design.

[21]  Mark C. Johnson,et al.  Software design for low power , 1997 .

[22]  Anantha P. Chandrakasan,et al.  Low Power Digital CMOS Design , 1995 .

[23]  Steven S. Muchnick,et al.  Advanced Compiler Design and Implementation , 1997 .

[24]  Mahmut T. Kandemir,et al.  Improving locality using loop and data transformations in an integrated framework , 1998, Proceedings. 31st Annual ACM/IEEE International Symposium on Microarchitecture.

[25]  Bryan D. Ackland,et al.  High performance DSPs - what's hot and what's not? , 1998, ISLPED '98.

[26]  K. Ghose,et al.  Analytical energy dissipation models for low power caches , 1997, Proceedings of 1997 International Symposium on Low Power Electronics and Design.

[27]  Rajendran Panda,et al.  Emerging power management tools for processor design , 1998, Proceedings. 1998 International Symposium on Low Power Electronics and Design (IEEE Cat. No.98TH8379).

[28]  Francky Catthoor,et al.  Custom Memory Management Methodology: Exploration of Memory Organisation for Embedded Multimedia System Design , 1998 .

[29]  Dirk Grunwald,et al.  Predictive sequential associative cache , 1996, Proceedings. Second International Symposium on High-Performance Computer Architecture.