A Sub-mW Fractional- ${N}$ ADPLL With FOM of −246 dB for IoT Applications

This paper presents a sub-mW fractional-<inline-formula> <tex-math notation="LaTeX">${N}$ </tex-math></inline-formula> all-digital phase-locked loop (ADPLL) with scalable power consumption, which achieves an figure of merit (FOM) of −246 dB. The proposed 10-b ultralow-power isolated constant-slope digital-to-time converter (DTC) achieves a 580-fs resolution and a measured integral nonlinearity (INL) of 870 fs with 0.14-mW power consumption at 52 MS/s. A narrow-range time amplifier (TA)-time-to-digital converter (TDC) with gain calibration minimizes both the in-band phase noise degradation and the loop-bandwidth variation. In addition, a coarse-DPLL is introduced with dead-zone function, which reduces the phase lock time to 4.2 <inline-formula> <tex-math notation="LaTeX">$\mu \text{s}$ </tex-math></inline-formula> at a 13-MHz frequency error. The coarse-DPLL monitors large frequency and phase jump in the background while consuming almost zero power. In an ultralow power mode, the proposed fractional-<inline-formula> <tex-math notation="LaTeX">${N}$ </tex-math></inline-formula> ADPLL consumes a 0.65-mW power with a 26-MHz reference. A rms jitter of 1.00 ps and −50-dBc in-band fractional spur are achieved with a −242-dB FOM. In high-performance mode, a reference doubler is utilized, the jitter and spurs can be improved to 535 fs and −56 dBc, respectively, while consuming 0.98 mW. The proposed ADPLL with scalable power and jitter performance can be utilized for Internet-of-Things (IoT) applications, such as Bluetooth low energy (BLE) and Wi-Fi networks.

[1]  Eric A. M. Klumperink,et al.  A Sensitive Method to Measure the Integral Nonlinearity of a Digital-to-Time Converter Based on Phase Modulation , 2015, IEEE Transactions on Circuits and Systems II: Express Briefs.

[2]  Teerachot Siriburanon,et al.  A 0.5V 1.6mW 2.4GHz fractional-N all-digital PLL for Bluetooth LE with PVT-insensitive TDC using switched-capacitor doubler in 28nm CMOS , 2017, 2017 Symposium on VLSI Circuits.

[3]  Kenichi Okada,et al.  A 3.6 GHz Low-Noise Fractional-N Digital PLL Using SAR-ADC-Based TDC , 2016, IEEE Journal of Solid-State Circuits.

[4]  Kathleen Philips,et al.  24.7 A 673µW 1.8-to-2.5GHz dividerless fractional-N digital PLL with an inherent frequency-capture capability and a phase-dithering spur mitigation for IoT applications , 2017, 2017 IEEE International Solid-State Circuits Conference (ISSCC).

[5]  Changsik Yoo,et al.  A Fast automatic frequency calibration (AFC) scheme for phase-locked loop (PLL) frequency synthesizer , 2009, 2009 IEEE Radio Frequency Integrated Circuits Symposium.

[6]  K. Muhammad,et al.  All-digital PLL and transmitter for mobile phones , 2005, IEEE Journal of Solid-State Circuits.

[7]  Po-Chun Huang,et al.  A Fractional-N Divider-Less Phase-Locked Loop With a Subsampling Phase Detector , 2014, IEEE Journal of Solid-State Circuits.

[8]  Kathleen Philips,et al.  9.8 An 860μW 2.1-to-2.7GHz all-digital PLL-based frequency modulator with a DTC-assisted snapshot TDC for WPAN (Bluetooth Smart and ZigBee) applications , 2014, 2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC).

[9]  Kathleen Philips,et al.  An Ultra-Low Power 1.7-2.7 GHz Fractional-N Sub-Sampling Digital Frequency Synthesizer and Modulator for IoT Applications in 40 nm CMOS , 2017, IEEE Transactions on Circuits and Systems I: Regular Papers.

[10]  Ahmed Elkholy,et al.  A 3.7 mW Low-Noise Wide-Bandwidth 4.5 GHz Digital Fractional-N PLL Using Time Amplifier-Based TDC , 2015, IEEE Journal of Solid-State Circuits.

[11]  Jan Craninckx,et al.  A 10-bit, 550-fs step Digital-to-Time Converter in 28nm CMOS , 2014, ESSCIRC 2014 - 40th European Solid State Circuits Conference (ESSCIRC).

[12]  Hong-June Park,et al.  A 0.63ps resolution, 11b pipeline TDC in 0.13µm CMOS , 2011, 2011 Symposium on VLSI Circuits - Digest of Technical Papers.

[13]  Kang-Yoon Lee,et al.  A CMOS dual-band fractional-n synthesizer with reference doubler and compensated charge pump , 2004, 2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519).

[14]  Giovanni Marzin,et al.  A 2.9-to-4.0GHz fractional-N digital PLL with bang-bang phase detector and 560fsrms integrated jitter at 4.5mW power , 2011, 2011 IEEE International Solid-State Circuits Conference.

[15]  A.A. Abidi,et al.  Phase Noise and Jitter in CMOS Ring Oscillators , 2006, IEEE Journal of Solid-State Circuits.

[16]  Jan Craninckx,et al.  A 9.2–12.7 GHz Wideband Fractional-N Subsampling PLL in 28 nm CMOS With 280 fs RMS Jitter , 2015, IEEE Journal of Solid-State Circuits.

[17]  Eric A. M. Klumperink,et al.  A High-Linearity Digital-to-Time Converter Technique: Constant-Slope Charging , 2015, IEEE Journal of Solid-State Circuits.

[18]  Nenad Pavlovic,et al.  A 5.3GHz digital-to-time-converter-based fractional-N all-digital PLL , 2011, 2011 IEEE International Solid-State Circuits Conference.

[19]  Shinwoong Kim,et al.  A 14-nm 0.14-psrms Fractional-N Digital PLL With a 0.2-ps Resolution ADC-Assisted Coarse/Fine-Conversion Chopping TDC and TDC Nonlinearity Calibration , 2017, IEEE Journal of Solid-State Circuits.

[20]  A.A. Abidi,et al.  A 9 b, 1.25 ps Resolution Coarse–Fine Time-to-Digital Converter in 90 nm CMOS that Amplifies a Time Residue , 2008, IEEE Journal of Solid-State Circuits.

[21]  Jing-Hong Conan Zhan,et al.  28.2 A 0.29mm2 frequency synthesizer in 40nm CMOS with 0.19psrms jitter and <-100dBc reference spur for 802.11ac , 2014, 2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC).

[22]  Teerachot Siriburanon,et al.  A 0.5-V 1.6-mW 2.4-GHz Fractional-N All-Digital PLL for Bluetooth LE With PVT-Insensitive TDC Using Switched-Capacitor Doubler in 28-nm CMOS , 2018, IEEE Journal of Solid-State Circuits.

[23]  Giovanni Marzin,et al.  2.9 A Background calibration technique to control bandwidth in digital PLLs , 2014, 2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC).

[24]  Kenichi Okada,et al.  A Fractional-N Sub-Sampling PLL using a Pipelined Phase-Interpolator With an FoM of -250 dB , 2016, IEEE Journal of Solid-State Circuits.

[25]  Kenichi Okada,et al.  An ADPLL-centric bluetooth low-energy transceiver with 2.3mW interference-tolerant hybrid-loop receiver and 2.9mW single-point polar transmitter in 65nm CMOS , 2018, 2018 IEEE International Solid - State Circuits Conference - (ISSCC).

[26]  Ahmed Elkholy,et al.  Low-Jitter Multi-Output All-Digital Clock Generator Using DTC-Based Open Loop Fractional Dividers , 2018, IEEE Journal of Solid-State Circuits.

[27]  Jae-Yoon Sim,et al.  A 1 GHz ADPLL With a 1.25 ps Minimum-Resolution Sub-Exponent TDC in 0.18 $\mu$ m CMOS , 2010, IEEE Journal of Solid-State Circuits.

[28]  Li Lin,et al.  9.4 A 28nm CMOS digital fractional-N PLL with −245.5dB FOM and a frequency tripler for 802.11abgn/ac radio , 2015, 2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers.

[29]  Poras T. Balsara,et al.  Digitally controlled oscillator (DCO)-based architecture for RF frequency synthesis in a deep-submicrometer CMOS Process , 2003, IEEE Trans. Circuits Syst. II Express Briefs.