A Systolic Array Architecture for Fast Decoding of One-Point AG Codes and Scheduling of Parallel Processing on It

Since before we have proposed a systolic array architecture for implementing fast decoding algorithm of one point AG codes. In this paper we propose a revised architecture which is as its main framework a one-dimensional systolic array, in details, composed of a three-dimensional arrangement of processing units called cells, and present a method of complete scheduling on it, where not only our scheme has linear time complexity but also it satisfies restriction to local communication between nearest cells so that transmission delay is drastically reduced.

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