Exploiting Self-Reconfiguration Capability to Improve SRAM-based FPGA Robustness in Space and Avionics Applications

This article presents a novel configuration scrubbing core, used for internal detection and correction of radiation-induced configuration single and multiple bit errors, without requiring external scrubbing. The proposed technique combines the benefits of fast radiation-induced fault detection with fast restoration of the device functionality and small area and power overheads. Experimental results demonstrate that the novel approach significantly improves the availability in hostile radiation environments of FPGA-based designs. When implemented using a Xilinx XC2V1000 Virtex-II device, the presented technique detects and corrects single bit upsets and double, triple and quadruple multi bit upsets, occupying just 1488 slices and dissipating less than 30 mW at a 50MHz running frequency.

[1]  D. Bortolato,et al.  Errata to “Identification and Classification of Single-Event Upsets in the Configuration Memory of SRAM-Based FPGAs” , 2003 .

[2]  A. Lesea,et al.  Effectiveness of Internal Versus External SEU Scrubbing Mitigation Strategies in a Xilinx FPGA: Design, Test, and Analysis , 2008, IEEE Transactions on Nuclear Science.

[3]  M. Caffrey,et al.  Correcting single-event upsets through virtex partial configuration , 2000 .

[4]  K. Chapman SEU Strategies for Virtex-5 Devices , 2010 .

[5]  S. Katkoori,et al.  Selective triple Modular redundancy (STMR) based single-event upset (SEU) tolerant synthesis for FPGAs , 2004, IEEE Transactions on Nuclear Science.

[6]  P. Graham,et al.  Radiation-induced multi-bit upsets in SRAM-based FPGAs , 2005, IEEE Transactions on Nuclear Science.

[7]  C. Carmichael,et al.  Comparison of Xilinx Virtex-II FPGA SEE sensitivities to protons and heavy ions , 2004, IEEE Transactions on Nuclear Science.

[8]  C. Carmichael,et al.  Dynamic testing of Xilinx Virtex-II field programmable gate array (FPGA) input/output blocks (IOBs) , 2004, IEEE Transactions on Nuclear Science.

[9]  M. Wirthlin,et al.  Fault Tolerant ICAP Controller for High-Reliable Internal Scrubbing , 2008, 2008 IEEE Aerospace Conference.

[10]  M. Wirthlin,et al.  SEU-induced persistent error propagation in FPGAs , 2005, IEEE Transactions on Nuclear Science.

[11]  I. Xilinx,et al.  Virtex-II Platform FPGA User Guide , 2002 .

[12]  Wei Tseng Correcting Single-Event Upsets with a Self-Hosting Configuration Management Core , 2000 .

[13]  Mehdi Baradaran Tahoori,et al.  Analytical Techniques for Soft Error Rate Modeling and Mitigation of FPGA-Based Designs , 2007, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[14]  Maya Gokhale,et al.  Dynamic reconfiguration for management of radiation-induced faults in FPGAs , 2004, 18th International Parallel and Distributed Processing Symposium, 2004. Proceedings..

[15]  Gustavo Ribeiro Alves,et al.  A Framework for Self-Healing Radiation-Tolerant Implementations on Reconfigurable FPGAs , 2007, 2007 IEEE Design and Diagnostics of Electronic Circuits and Systems.

[16]  M. Caffrey,et al.  Domain Crossing Errors: Limitations on Single Device Triple-Modular Redundancy Circuits in Xilinx FPGAs , 2007, IEEE Transactions on Nuclear Science.

[17]  Erold W. Hinds,et al.  Error-correction coding , 1996 .

[18]  C. Carmichael,et al.  SEU mitigation testing of Xilinx Virtex II FPGAs , 2003, 2003 IEEE Radiation Effects Data Workshop.

[19]  Marco Lanuzza,et al.  An Efficient and Low-Cost Design Methodology to Improve SRAM-Based FPGA Robustness in Space and Avionics Applications , 2009, ARC.

[20]  P. Sundararajan,et al.  Consequences and Categories of SRAM FPGA Configuration SEUs , 2003 .

[21]  Paul Graham,et al.  Evaluation of power costs in applying TMR to FPGA designs. , 2004 .

[22]  Milan Vasilko,et al.  On Feasibility of FPGA Bitstream Compression During Placement and Routing , 2006, 2006 International Conference on Field Programmable Logic and Applications.

[23]  Sammy Kayali NASA Electronic Parts and Packaging Program , 2000 .

[24]  Carl Carmichael Virtex FPGA series configuration and readback , 1999 .

[25]  Gary Swift,et al.  Initial Single Event Effects Testing of the Xilinx Virtex-4 Field Programmable Gate Array , 2007 .