A Fast-Locking All-Digital Phase-Locked Loop With Dynamic Loop Bandwidth Adjustment

A fast-locking all-digital phase-locked loop (ADPLL) including a fast-locking unit, a multi-level bang-bang phase detector (ML-BBPD), a dynamic gain adjustment controller (DGAC), and a digitally controlled oscillator (DCO) is presented. The ML-BBPD provides multi-level outputs with different phase errors. According to the detection results of ML-BBPD, the DGAC can adjust the dynamic integral gain of digital loop filter to provide four different operation modes and keep the ADPLL always in stable operation for fast-locking procedure. The DCO with loading compensation circuit can decrease the difference of tuning range in 13 bands less than 25%. Implemented with a 0.18- μm CMOS technology, the area of the core circuit is 0.7735 mm2 and the total power consumption is 35 mW from a 1.8 V supply voltage at 1.25 GHz. The ADPLL can generate output frequencies from 253.9 MHz to 1.367 GHz with 12-phase output clocks. Experimental result shows that the locking time can be accomplished in 2.9184 μs, i.e., 57 cycles with a 19.53125 MHz reference clock. The phase noise is -108.77 dBc/Hz at 1 MHz frequency offset, and measured rms jitter and peak-to-peak jitter are 8.884 ps and 32.5 ps respectively.

[1]  Salvatore Levantino,et al.  Noise Analysis and Minimization in Bang-Bang Digital PLLs , 2009, IEEE Transactions on Circuits and Systems II: Express Briefs.

[2]  John T. Stonick,et al.  A digital clock and data recovery architecture for multi-gigabit/s binary links , 2005, Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005..

[3]  Hyung Seok Kim,et al.  A reconfigurable distributed all-digital clock generator core with SSC and skew correction in 22nm high-k tri-gate LP CMOS , 2012, 2012 IEEE International Solid-State Circuits Conference.

[4]  J.A. Tierno,et al.  A Wide Power Supply Range, Wide Tuning Range, All Static CMOS All Digital PLL in 65 nm SOI , 2008, IEEE Journal of Solid-State Circuits.

[5]  K. Muhammad,et al.  All-digital PLL and transmitter for mobile phones , 2005, IEEE Journal of Solid-State Circuits.

[6]  Ching-Yuan Yang,et al.  A $\Delta{-}\Sigma$ PLL-Based Spread-Spectrum Clock Generator With a Ditherless Fractional Topology , 2009, IEEE Transactions on Circuits and Systems I: Regular Papers.

[7]  Dmytro Cherniak,et al.  digPLL-Lite: A Low-Complexity, Low-Jitter Fractional-N Digital PLL Architecture , 2013, IEEE Journal of Solid-State Circuits.

[8]  Suhwan Kim,et al.  A 2.8Gb/s All-Digital CDR with a 10b Monotonic DCO , 2007, 2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

[9]  Wei-Zen Chen,et al.  A 7.1 mW, 10 GHz All Digital Frequency Synthesizer With Dynamically Reconfigured Digital Loop Filter in 90 nm CMOS Technology , 2010, IEEE Journal of Solid-State Circuits.

[10]  Hyung-Jin Lee,et al.  A TDC-less ADPLL with 200-to-3200MHz range and 3mW power dissipation for mobile SoC clocking in 22nm CMOS , 2012, 2012 IEEE International Solid-State Circuits Conference.

[11]  Giovanni Marzin,et al.  2.9 A Background calibration technique to control bandwidth in digital PLLs , 2014, 2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC).

[12]  Chih-Kong Ken Yang,et al.  Technique to Reduce the Resolution Requirement of Digitally Controlled Oscillators for Digital PLLs , 2007, IEEE Transactions on Circuits and Systems II: Express Briefs.

[13]  Shen-Iuan Liu,et al.  A 40-GHz Fast-Locked All-Digital Phase-Locked Loop Using a Modified Bang-Bang Algorithm , 2011, IEEE Transactions on Circuits and Systems II: Express Briefs.

[14]  Seongdo Kim,et al.  A 4-GHz All Digital PLL With Low-Power TDC and Phase-Error Compensation , 2012, IEEE Transactions on Circuits and Systems I: Regular Papers.

[15]  Tobias G. Noll,et al.  Theory and implementation of digital bang-bang frequency synthesizers for high speed serial communications , 2007 .

[16]  Orla Feely,et al.  Binary Phase Detector Gain in Bang-Bang Phase-Locked Loops With DCO Jitter , 2010, IEEE Transactions on Circuits and Systems II: Express Briefs.

[17]  Pavan Kumar Hanumolu,et al.  A Design Procedure for All-Digital Phase-Locked Loops Based on a Charge-Pump Phase-Locked-Loop Analogy , 2007, IEEE Transactions on Circuits and Systems II: Express Briefs.

[18]  René Schüffny,et al.  A Fast-Locking ADPLL With Instantaneous Restart Capability in 28-nm CMOS Technology , 2013, IEEE Transactions on Circuits and Systems II: Express Briefs.

[19]  Roberto Nonis,et al.  A 1.4psrms-period-jitter TDC-less fractional-N digital PLL with digitally controlled ring oscillator in 65nm CMOS , 2010, 2010 IEEE International Solid-State Circuits Conference - (ISSCC).

[20]  Shen-Iuan Liu,et al.  A 1.25GHz fast-locked all-digital phase-locked loop with supply noise suppression , 2010, Proceedings of 2010 International Symposium on VLSI Design, Automation and Test.

[21]  Giovanni Marzin,et al.  A 2.9–4.0-GHz Fractional-N Digital PLL With Bang-Bang Phase Detector and 560-${\rm fs}_{\rm rms}$ Integrated Jitter at 4.5-mW Power , 2011, IEEE Journal of Solid-State Circuits.

[22]  Robert Bogdan Staszewski,et al.  LMS-based calibration of an RF digitally controlled oscillator for mobile phones , 2006, IEEE Transactions on Circuits and Systems II: Express Briefs.

[23]  Chulwoo Kim,et al.  A 2.4 GHz 0.1-Fref-Bandwidth All-Digital Phase-Locked Loop With Delay-Cell-Less TDC , 2013, IEEE Transactions on Circuits and Systems I: Regular Papers.

[24]  Deok-Soo Kim,et al.  A 0.3–1.4 GHz All-Digital Fractional-N PLL With Adaptive Loop Gain Controller , 2010, IEEE Journal of Solid-State Circuits.

[25]  Ching-Yuan Yang,et al.  A Delta-Sigma PLL-Based Spread-Spectrum Clock Generator With a Ditherless Fractional Topology , 2009, IEEE Trans. Circuits Syst. I Regul. Pap..

[26]  Enrico Temporiti,et al.  A 3 GHz Fractional All-Digital PLL With a 1.8 MHz Bandwidth Implementing Spur Reduction Techniques , 2009, IEEE Journal of Solid-State Circuits.

[27]  Poras T. Balsara,et al.  All-Digital PLL With Ultra Fast Settling , 2007, IEEE Transactions on Circuits and Systems II: Express Briefs.

[28]  Pavan Kumar Hanumolu,et al.  A 0.6GHz to 2GHz Digital PLL with Wide Tracking Range , 2007, 2007 IEEE Custom Integrated Circuits Conference.

[29]  Ching-Yuan Yang,et al.  A 2.5-Gb/s DLL-Based Burst-Mode Clock and Data Recovery Circuit With $4\times$ Oversampling , 2015, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[30]  Shalabh Gupta,et al.  Tradeoffs between settling time and jitter in phase locked loops , 2013, 2013 IEEE 56th International Midwest Symposium on Circuits and Systems (MWSCAS).

[31]  Robert B. Staszewski,et al.  Spurious-Free Time-to-Digital Conversion in an ADPLL Using Short Dithering Sequences , 2011, IEEE Transactions on Circuits and Systems I: Regular Papers.

[32]  Nicola Da Dalt.  A design-oriented study of the nonlinear dynamics of digital bang-bang PLLs , 2005, IEEE Trans. Circuits Syst. I Regul. Pap..

[33]  B. Razavi,et al.  A 2.6-GHz/5.2-GHz frequency synthesizer in 0.4-/spl mu/m CMOS technology , 2000, 1999 Symposium on VLSI Circuits. Digest of Papers (IEEE Cat. No.99CH36326).

[34]  Pavan Kumar Hanumolu,et al.  A Digital PLL With a Stochastic Time-to-Digital Converter , 2006, IEEE Transactions on Circuits and Systems I: Regular Papers.