A 16-Gbps 9mW Transmitter with FFE in 90nm CMOS Technology for Off-Chip Communication

This paper presents a low power 16 Gbps backplane transmitter for chip-to-chip communication, designed and optimized in 90nm CMOS process with supply voltage of 1V. The proposed 3-tap transmitter incorporates a new quarter-rate architecture for feed-forward equalization at the transmitter end. Key features of this architecture are: most of the circuit modules operate at quarter-rate and data serializer as well as feed forward equalizer are merged together in one module. Both the features enable low power operation. Simulation results show that 16 Gbps data rate can be achieved over 30cm FR4 line consuming 9mW average power. Power per Gbps consumed by the proposed architecture is 62% less as compared to state of the art FFE equalizer realized in the same technology.

[1]  Joe Caroselli,et al.  A 4.8-6.4 Gbps serial link for back-plane applications using decision feedback equalization , 2004, Proceedings of the IEEE 2004 Custom Integrated Circuits Conference (IEEE Cat. No.04CH37571).

[2]  Joungho Kim,et al.  Over GHz low-power RF clock distribution for a multiprocessor digital system , 2001, 2001 Proceedings. 51st Electronic Components and Technology Conference (Cat. No.01CH37220).

[3]  Maryam Shojaei Baghini,et al.  A process variation tolerant, high-speed and low-power current mode signaling scheme for on-chip interconnects , 2009, GLSVLSI '09.

[4]  M. K. Iyer,et al.  High frequency modelling of power/ground plane pairs with lossy substrates , 2000, IEEE 9th Topical Meeting on Electrical Performance of Electronic Packaging (Cat. No.00TH8524).

[5]  Daniel J. Friedman,et al.  A 12-Gb/s 11-mW Half-Rate Sampled 5-Tap Decision Feedback Equalizer With Current-Integrating Summers in 45-nm SOI CMOS Technology , 2009, IEEE J. Solid State Circuits.

[6]  류웅환,et al.  Over GHz low-power RF clock distribution for a multi-processor digital system = 다중 프로세서 디지털 시스템을 위한 기가헤르쯔급 RF 클럭 분배 , 2001 .

[7]  Takashi Masuda,et al.  A 250mW Full-Rate 10Gb/s Transceiver Core in 90nm CMOS Using a Tri-State Binary PD with 100ps Gated Digital Output , 2007, 2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

[8]  Dao-Long Chen,et al.  A 1.25 Gb/s, 460 mW CMOS transceiver for serial data communication , 1997, 1997 IEEE International Solids-State Circuits Conference. Digest of Technical Papers.

[9]  Jri Lee,et al.  A 21-Gb/s 87-mW Transceiver With FFE/DFE/Analog Equalizer in 65-nm CMOS Technology , 2010, IEEE Journal of Solid-State Circuits.

[10]  Hong-June Park,et al.  An analytic decision method for the feed-forward equalizer tap-coefficients at transmitter , 2009, 2009 International SoC Design Conference (ISOCC).

[11]  Jri Lee,et al.  A 10Gb/s CMOS adaptive equalizer for backplane applications , 2005, ISSCC. 2005 IEEE International Digest of Technical Papers. Solid-State Circuits Conference, 2005..