Minimizing N-Detect Tests for Combinational Circuits
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[1] Oscar H. Ibarra,et al. Polynomially Complete Fault Detection Problems , 1975, IEEE Transactions on Computers.
[2] R. G. Bennetts,et al. Defect-Oriented Testing , 1995 .
[3] Edward J. McCluskey,et al. Stuck-fault tests vs. actual defects , 2000, Proceedings International Test Conference 2000 (IEEE Cat. No.00CH37159).
[4] M. Ray Mercer,et al. A new ATPG algorithm to limit test set size and achieve multiple detections of all faults , 2002, Proceedings 2002 Design, Automation and Test in Europe Conference and Exhibition.
[5] M. Ray Mercer,et al. An optimal test pattern selection method to improve the defect coverage , 2005, IEEE International Conference on Test, 2005..
[6] Tsutomu Sasao,et al. On the adders with minimum tests , 1997, Proceedings Sixth Asian Test Symposium (ATS'97).
[7] David Bryan,et al. Combinational profiles of sequential benchmark circuits , 1989, IEEE International Symposium on Circuits and Systems,.
[8] Michael H. Schulz,et al. Improved deterministic test pattern generation with applications to redundancy identification , 1989, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[9] Dong Sam Ha,et al. HOPE: an efficient parallel fault simulator for synchronous sequential circuits , 1992, DAC '92.
[10] Irith Pomeranz,et al. Cost-Effective Generation of Minimal Test Sets for Stuck-at Faults in Combinational Logic Circuits , 1993, 30th ACM/IEEE Design Automation Conference.
[11] Sudhakar M. Reddy,et al. Complete Test Sets for Logic Functions , 1973, IEEE Transactions on Computers.
[12] Hideo Fujiwara. Computational complexity of controllability/observability problems for combinational circuits , 1988, [1988] The Eighteenth International Symposium on Fault-Tolerant Computing. Digest of Papers.
[13] Vishwani D. Agrawal,et al. A Reduced Complexity Algorithm for Minimizing N-Detect Tests , 2007, 20th International Conference on VLSI Design held jointly with 6th International Conference on Embedded Systems (VLSID'07).
[14] S. B. Akers,et al. On the Role of Independent Fault Sets in the Generation of Minimal Test Sets , 1987 .
[15] R. D. Blanton,et al. Analyzing the effectiveness of multiple-detect test sets , 2003, International Test Conference, 2003. Proceedings. ITC 2003..
[16] Fei Su,et al. Test Planning and Test Resource Optimization for Droplet-Based Microfluidic Systems , 2004, Proceedings. Ninth IEEE European Test Symposium, 2004. ETS 2004..
[17] Irith Pomeranz,et al. Forming N-detection test sets from one-detection test sets without test generation , 2005, IEEE International Conference on Test, 2005..
[18] Sheldon B. Akers,et al. Universal Test Sets for Logic Networks , 1972, IEEE Transactions on Computers.
[19] Prabhakar Raghavan,et al. Randomized rounding: A technique for provably good algorithms and algorithmic proofs , 1985, Comb..
[20] Sheldon B. Akers,et al. On the Complexity of Estimating the Size of a Test Set , 1984, IEEE Transactions on Computers.
[21] Vishwani D. Agrawal,et al. INDEPENDENCE FAULT COLLAPSING , 2005 .
[22] Irith Pomeranz,et al. On the use of fault dominance in n-detection test generation , 2001, Proceedings 19th IEEE VLSI Test Symposium. VTS 2001.
[23] Bozena Kaminska,et al. A new dynamic test vector compaction for automatic test pattern generation , 1994, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[24] Kalyana R. Kantipudi. On the size and generation of minimal N-detection tests , 2006, 19th International Conference on VLSI Design held jointly with 5th International Conference on Embedded Systems Design (VLSID'06).
[25] Edward J. McCluskey,et al. An experimental chip to evaluate test techniques experiment results , 1995, Proceedings of 1995 IEEE International Test Conference (ITC).
[26] V. Agrawal,et al. Spectral RTL Test Generation for Gate-Level Stuck-at Faults , 2006, 2006 15th Asian Test Symposium.
[27] M. Ray Mercer,et al. Excitation, observation, and ELF-MD: optimization criteria for high quality test sets , 2004, 22nd IEEE VLSI Test Symposium, 2004. Proceedings..
[28] Vishwani D. Agrawal,et al. Essentials of electronic testing for digital, memory, and mixed-signal VLSI circuits [Book Review] , 2000, IEEE Circuits and Devices Magazine.
[29] Yusuke Matsunaga. MINT-An Exact Algorithm for Finding Minimum Test Set (Special Section on VLSI Design and CAD Algorithms) , 1993 .
[30] D. Mitra,et al. Convergence and finite-time behavior of simulated annealing , 1985, 1985 24th IEEE Conference on Decision and Control.
[31] Alok S. Doshi,et al. Independence Fault Collapsing and Concurrent Test Generation , 2006 .
[32] Ronald L. Rivest,et al. Introduction to Algorithms , 1990 .
[33] Irith Pomeranz,et al. COMPACTEST: a method to generate compact test sets for combinational circuits , 1993, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[34] John P. Hayes,et al. Unveiling the ISCAS-85 Benchmarks: A Case Study in Reverse Engineering , 1999, IEEE Des. Test Comput..
[35] Narendra Karmarkar,et al. A new polynomial-time algorithm for linear programming , 1984, STOC '84.
[36] David E. Goldberg,et al. Genetic Algorithms in Search Optimization and Machine Learning , 1988 .
[37] Sreejit Chakravarty,et al. Experimental evaluation of scan tests for bridges , 2002, Proceedings. International Test Conference.
[38] Raja K. K. R. Sandireddy,et al. Hierarchical Fault Collapsing for Logic Circuits , 2005 .
[39] Paulo F. Flores,et al. An exact solution to the minimum size test pattern problem , 1998, Proceedings International Conference on Computer Design. VLSI in Computers and Processors (Cat. No.98CB36273).
[40] Melvin A. Breuer,et al. Digital systems testing and testable design , 1990 .
[41] M. Ray Mercer,et al. Balanced excitation and its effect on the fortuitous detection of dynamic defects , 2004, Proceedings Design, Automation and Test in Europe Conference and Exhibition.
[42] Warren P. Adams,et al. A Reformulation-Linearization Technique for Solving Discrete and Continuous Nonconvex Problems , 1998 .
[43] Prabhakar Goel,et al. An Implicit Enumeration Algorithm to Generate Tests for Combinational Logic Circuits , 1981, IEEE Transactions on Computers.
[44] Kozo Kinoshita,et al. On test generation with a limited number of tests , 1999, Proceedings Ninth Great Lakes Symposium on VLSI.
[45] Edward J. McCluskey. Quality and single-stuck faults , 1993, Proceedings of IEEE International Test Conference - (ITC).
[46] Enamul Amyeen,et al. Evaluation of the quality of N-detect scan ATPG patterns on a processor , 2004, 2004 International Conferce on Test.
[47] Krishnendu Chakrabarty,et al. Test resource optimization for multi-site testing of SOCs under ATE memory depth constraints , 2002, Proceedings. International Test Conference.
[48] Jinkyu Lee,et al. Evaluation of test metrics: stuck-at, bridge coverage estimate and gate exhaustive , 2006, 24th IEEE VLSI Test Symposium.
[49] David S. Johnson,et al. Computers and Intractability: A Guide to the Theory of NP-Completeness , 1978 .
[50] Krishnendu Chakrabarty,et al. Test Data Compression and Test Resource Partitioning for System-on-a-Chip Using Frequency-Directed Run-Length (FDR) Codes , 2003, IEEE Trans. Computers.
[51] Y.T. Hou,et al. Path Selection and Rate Allocation for Video Streaming in Multihop Wireless Networks , 2006, MILCOM 2006 - 2006 IEEE Military Communications conference.
[52] Michael H. Schulz,et al. SOCRATES: a highly efficient automatic test pattern generation system , 1988, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[53] Yiorgos Makris,et al. Independent test sequence compaction through integer programming , 2003, Proceedings 21st International Conference on Computer Design.
[54] Ahmad A. Al-Yamani,et al. ELF-Murphy data on defects and tests sets , 2004, 22nd IEEE VLSI Test Symposium, 2004. Proceedings..
[55] R. Kipp Martin,et al. Large scale linear and integer optimization - a unified approach , 1998 .
[56] M. M. Flood. ON THE HITCHCOCK DISTRIBUTION PROBLEM , 1953 .
[57] Vishwani D. Agrawal,et al. Diagnostic and detection fault collapsing for multiple output circuits , 2005, Design, Automation and Test in Europe.
[58] Janusz Rajski,et al. Impact of multiple-detect test patterns on product quality , 2003, International Test Conference, 2003. Proceedings. ITC 2003..
[59] P. Goel. Test Generation and Dynamic Compaction of Tests , 1979 .
[60] Jau-Shien Chang,et al. Test set compaction for combinational circuits , 1992, Proceedings First Asian Test Symposium (ATS `92).
[61] Irith Pomeranz,et al. Stuck-at tuple-detection: a fault model based on stuck-at faults for improved defect coverage , 1998, Proceedings. 16th IEEE VLSI Test Symposium (Cat. No.98TB100231).
[62] Edward J. McCluskey,et al. Gate exhaustive testing , 2005, IEEE International Conference on Test, 2005..
[63] Krishnendu Chakrabarty,et al. Test Resource Partitioning for System-on-a-Chip , 2002, Frontiers in electronic testing.
[64] M. Ray Mercer,et al. Defect-Oriented Testing and Defective-Part-Level Prediction , 2001, IEEE Des. Test Comput..
[65] P. K. Gupta,et al. Linear programming and theory of games , 1979 .
[66] Edward J. McCluskey,et al. MINVDD testing for weak CMOS ICs , 2001, Proceedings 19th IEEE VLSI Test Symposium. VTS 2001.
[67] R. D. Blanton,et al. Multiple-detect ATPG based on physical neighborhoods , 2006, 2006 43rd ACM/IEEE Design Automation Conference.
[68] Manoj Sachdev. Defect Oriented Testing for CMOS Analog and Digital Circuits , 1997 .
[69] Dorit S. Hochbaum,et al. An optimal test compression procedure for combinational circuits , 1996, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[70] Enamul Amyeen,et al. An experimental study of N-detect scan ATPG patterns on a processor , 2004, 22nd IEEE VLSI Test Symposium, 2004. Proceedings..
[71] Paolo Prinetto,et al. New static compaction techniques of test sequences for sequential circuits , 1997, Proceedings European Design and Test Conference. ED & TC 97.
[72] S.B. Akers,et al. Test counting: a tool for VLSI testing , 1989, IEEE Design & Test of Computers.
[73] Venkatram Krishnaswamy,et al. A study of bridging defect probabilities on a Pentium (TM) 4 CPU , 2001, Proceedings International Test Conference 2001 (Cat. No.01CH37260).
[74] M. Ray Mercer,et al. REDO-random excitation and deterministic observation-first commercial experiment , 1999, Proceedings 17th IEEE VLSI Test Symposium (Cat. No.PR00146).
[75] J. Hayes,et al. Fault testing for reversible circuits , 2003, Proceedings. 21st VLSI Test Symposium, 2003..
[76] Hanif D. Sherali,et al. Cross-layer optimized multipath routing for video communications in wireless networks , 2007, IEEE Journal on Selected Areas in Communications.
[77] Vishwani D. Agrawal,et al. Concurrent Test Generation , 2005, 14th Asian Test Symposium (ATS'05).
[78] Yu Huang. On N-detect pattern set optimization , 2006, 7th International Symposium on Quality Electronic Design (ISQED'06).
[79] Raimund Ubar,et al. Fast static compaction of tests composed of independent sequences: basic properties and comparison of methods , 2002, 9th International Conference on Electronics, Circuits and Systems.
[80] Joao Marques-Silva. Integer Programming Models for Optimization Problems in Test Generation , 1998, ASP-DAC.
[81] Brian W. Kernighan,et al. AMPL: a mathematical programming language , 1989 .
[82] Janak H. Patel,et al. Test set compaction algorithms for combinational circuits , 1998, 1998 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (IEEE Cat. No.98CB36287).
[83] Kenneth Steiglitz,et al. Combinatorial Optimization: Algorithms and Complexity , 1981 .