A 1㎒ High Efficient, Two-Stage Interleaved Synchronous Buck CMOS DC-DC Converter

This paper presents a high efficient 3.3 ? 1V two-stage interleaved synchronous buck CMOS DC-DC converter designed with standard CMOS 0.35㎛ process parameter. The proposed circuit has a low output voltage ripple. To reduce the output voltage ripple, the duty cycle of the interleaved converter is fixed as D=0.5 by an input stage buck converter. It causes the best ripple cancelation of the output current ripple. The proposed circuit was simulated by HSPICE and the simulation results show that the efficiency of the proposed converter is more than 85% in the load current range of 125 ? 400㎃, and the peak-topeak output voltage ripple is measured as 10 ㎷ with the 1μF external output capacitor. From these results, the proposed circuit is adequate for the battery-operated system.

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