Rerouting: Scalable NoC self-optimization by distributed hardware-based connection reallocation

Networks-on-Chip (NoC) are the most promising candidates for scalable communication infrastructures in manycore architectures. To ensure scalability, distributed management of communication resources needs to replace centralized approaches. Hence, distributed adaptive routing schemes in combination with selection strategies are used to take semi-optimal routing decisions according to the current NoC utilization. Once these routing decisions are taken for guaranteed service connections, which are established for longer periods, the load situation can change during their lifetime. For such connections taken routing decisions might be poor at a later point in time due to dynamically changing communication workload. The proposed hardware-based mechanism called rerouting reacts on changing load conditions and reallocates existing connections transparently. This balances the NoC load and allows to increase the number of guaranteed service connections. Throughput and delay of existing connections can also be improved by rerouting. The concept is investigated using synthetic traffic patterns and distributed video processing applications. ASIC and FPGA synthesis results are presented to investigate the implementation costs.

[1]  Vincenzo Catania,et al.  Implementation and Analysis of a New Selection Strategy for Adaptive Routing in Networks-on-Chip , 2008, IEEE Transactions on Computers.

[2]  William J. Dally,et al.  Principles and Practices of Interconnection Networks , 2004 .

[3]  Luca Benini,et al.  NoC synthesis flow for customized domain specific multiprocessor systems-on-chip , 2005, IEEE Transactions on Parallel and Distributed Systems.

[4]  Vincenzo Catania,et al.  Neighbors-on-Path: A New Selection Strategy for On-Chip Networks , 2006, 2006 IEEE/ACM/IFIP Workshop on Embedded Systems for Real Time Multimedia.

[5]  Coniferous softwood.  GENERAL TERMS , 2003 .

[6]  Jürgen Becker,et al.  Providing multiple hard latency and throughput guarantees for packet switching networks on chip , 2013, Comput. Electr. Eng..

[7]  William J. Dally.  Virtual-channel flow control , 1990, ISCA '90.

[8]  Jürgen Teich,et al.  Hardware-assisted Decentralized Resource Management for Networks on Chip with QoS , 2012, 2012 IEEE 26th International Parallel and Distributed Processing Symposium Workshops & PhD Forum.

[9]  Stephen W. Keckler,et al.  Regional congestion awareness for load balance in networks-on-chip , 2008, 2008 IEEE 14th International Symposium on High Performance Computer Architecture.

[10]  Saad Mubeen,et al.  Designing Efficient Source Routing for Mesh Topology Network on Chip Platforms , 2010, 2010 13th Euromicro Conference on Digital System Design: Architectures, Methods and Tools.

[11]  Ran Ginosar,et al.  QNoC: QoS architecture and design process for network on chip , 2004, J. Syst. Archit..

[12]  Axel Jantsch,et al.  Guaranteed bandwidth using looped containers in temporally disjoint networks within the nostrum network on chip , 2004, Proceedings Design, Automation and Test in Europe Conference and Exhibition.

[13]  Loren Schwiebert,et al.  Performance Tuning of Adaptive Wormhole Routing through Selection Function Choice , 2002, J. Parallel Distributed Comput..

[14]  Ge-Ming Chiu,et al.  The Odd-Even Turn Model for Adaptive Routing , 2000, IEEE Trans. Parallel Distributed Syst..

[15]  Wolfgang Schröder-Preikschat,et al.  DistRM: Distributed resource management for on-chip many-core systems , 2011, 2011 Proceedings of the Ninth IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS).

[16]  Gerard J. M. Smit,et al.  An energy-efficient reconfigurable circuit-switched network-on-chip , 2005, 19th IEEE International Parallel and Distributed Processing Symposium.

[17]  Luis Gravano,et al.  Fully-adaptive routing: packet switching performance and wormhole algorithms , 1991, Proceedings of the 1991 ACM/IEEE Conference on Supercomputing (Supercomputing '91).

[18]  Kees Goossens,et al.  AEthereal network on chip: concepts, architectures, and implementations , 2005, IEEE Design & Test of Computers.

[19]  Jürgen Becker,et al.  A Scalable NoC Router Design Providing QoS Support Using Weighted Round Robin Scheduling , 2012, 2012 IEEE 10th International Symposium on Parallel and Distributed Processing with Applications.

[20]  Melanie L. Fulgham.  Performance of Chaos and Oblivious Routers Under Non-uniform Traffic , 1993 .

[21]  Altamiro Amadeu Susin,et al.  SoCIN: a parametric and scalable network-on-chip , 2003, 16th Symposium on Integrated Circuits and Systems Design, 2003. SBCCI 2003. Proceedings..

[22]  Saurabh Dighe,et al.  A 48-Core IA-32 Processor in 45 nm CMOS Using On-Die Message-Passing and DVFS for Performance and Power Scaling , 2011, IEEE Journal of Solid-State Circuits.

[23]  Alan Sussman,et al.  Decentralized resource management for multi-core desktop grids , 2010, 2010 IEEE International Symposium on Parallel & Distributed Processing (IPDPS).

[24]  Alain Greiner,et al.  A reconfigurable routing algorithm for a fault-tolerant 2D-Mesh Network-on-Chip , 2008, 2008 45th ACM/IEEE Design Automation Conference.

[25]  Luca Benini,et al.  Networks on Chips : A New SoC Paradigm , 2022 .

[26]  Radu Marculescu,et al.  DyAD - smart routing for networks-on-chip , 2004, Proceedings. 41st Design Automation Conference, 2004..

[27]  Kees G. W. Goossens,et al.  Congestion-Controlled Best-Effort Communication for Networks-on-Chip , 2007, 2007 Design, Automation & Test in Europe Conference & Exhibition.

[28]  David Blaauw,et al.  A highly resilient routing algorithm for fault-tolerant NoCs , 2009, 2009 Design, Automation & Test in Europe Conference & Exhibition.

[29]  Gerard J. M. Smit,et al.  A virtual channel network-on-chip for GT and BE traffic , 2006, IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures (ISVLSI'06).