Boolean factoring and decomposition of logic networks
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[1] Robert K. Brayton,et al. Improvements to Technology Mapping for LUT-Based FPGAs , 2007, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[2] Jason Cong,et al. Cut ranking and pruning: enabling a general and efficient FPGA mapping solution , 1999, FPGA '99.
[3] Jason Cong,et al. Improved SAT-based Boolean matching using implicants for LUT-based FPGAs , 2007, FPGA '07.
[4] Sze-Tsen Hu. ON THE DECOMPOSITION OF SWITCHING FUNCTIONS , 1961 .
[5] Yu Hu,et al. Exploiting symmetry in SAT-based boolean matching for heterogeneous FPGA technology mapping , 2007, 2007 IEEE/ACM International Conference on Computer-Aided Design.
[6] Tsutomu Sasao,et al. DECOMPOS : An integrated system for functional decomposition , 1998 .
[7] Majid Sarrafzadeh,et al. Complexity of the lookup-table minimization problem for FPGA technology mapping , 1994, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[8] Massoud Pedram,et al. A new canonical form for fast Boolean matching in logic synthesis and verification , 2005, Proceedings. 42nd Design Automation Conference, 2005..
[9] Richard M. Karp,et al. Minimization Over Boolean Graphs , 1962, IBM J. Res. Dev..
[10] Tsutomu Sasao,et al. Encoding of Boolean Functions and its Application to LUT Cascade Synthesis , 2002, IWLS.
[11] Alan Mishchenko,et al. Fast Boolean Matching for LUT Structures , 2007 .
[12] Karem A. Sakallah,et al. Constructive library-aware synthesis using symmetries , 2000, DATE '00.
[13] Robert K. Brayton,et al. Reducing structural bias in technology mapping , 2006, ICCAD-2005. IEEE/ACM International Conference on Computer-Aided Design, 2005..
[14] Yosinori Watanabe,et al. Logic decomposition during technology mapping , 1995, ICCAD.
[15] Robert K. Brayton,et al. DAG-aware AIG rewriting: a fresh look at combinational logic synthesis , 2006, 2006 43rd ACM/IEEE Design Automation Conference.
[16] Tsutomu Sasao,et al. Efficient computation of canonical form for boolean matching in large libraries , 2004, ASP-DAC 2004: Asia and South Pacific Design Automation Conference 2004 (IEEE Cat. No.04EX753).
[17] Robert K. Brayton,et al. Combinational and sequential mapping with priority cuts , 2007, 2007 IEEE/ACM International Conference on Computer-Aided Design.
[18] Russell Tessier,et al. BDD-based logic synthesis for LUT-based FPGAs , 2002, TODE.
[19] Valeria Bertacco,et al. The disjunctive decomposition of logic functions , 1997, 1997 Proceedings of IEEE International Conference on Computer Aided Design (ICCAD).
[20] Jason Cong,et al. DAOmap: a depth-optimal area optimization mapping algorithm for FPGA designs , 2004, IEEE/ACM International Conference on Computer Aided Design, 2004. ICCAD-2004..
[21] Karem A. Sakallah,et al. Constructive multi-level synthesis by way of functional properties , 2001 .
[22] Stephen Dean Brown,et al. FPGA technology mapping: a study of optimality , 2005, Proceedings. 42nd Design Automation Conference, 2005..
[23] Hiroshi Sawada,et al. Logic synthesis for look-up table based FPGAs using functional decomposition and support minimization , 1995, ICCAD.
[24] Alan Mishchenko,et al. A new-enhanced constructive decomposition and mapping algorithm , 2003, Proceedings 2003. Design Automation Conference (IEEE Cat. No.03CH37451).
[25] A. Mishchenko,et al. Factor Cuts , 2006, 2006 IEEE/ACM International Conference on Computer Aided Design.
[26] Andreas Kuehlmann,et al. Building a Better Boolean Matcher and Symmetry Detector , 2006, Proceedings of the Design Automation & Test in Europe Conference.
[27] H. A. Curtis,et al. A new approach to The design of switching circuits , 1962 .
[28] R. Brayton,et al. Improvements to Combinational Equivalence Checking , 2006, 2006 IEEE/ACM International Conference on Computer Aided Design.
[29] Peichen Pan,et al. A new retiming-based technology mapping algorithm for LUT-based FPGAs , 1998, FPGA '98.
[30] Ulf Schlichtmann,et al. Functional multiple-output decomposition with application to technology mapping for lookup table-based FPGAs , 1999, TODE.
[31] R. Brayton,et al. SAT-Based Logic Optimization and Resynthesis , 2007 .
[32] Marek A. Perkowski,et al. New multivalued functional decomposition algorithms based on MDDs , 2000, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[33] Malgorzata Marek-Sadowska,et al. Decomposition of Multiple-Valued Relations , 1997, ISMVL.
[34] Sean Safarpour,et al. Efficient SAT-based Boolean matching for FPGA technology mapping , 2006, 2006 43rd ACM/IEEE Design Automation Conference.
[35] Stephen Dean Brown,et al. Heuristics for Area Minimization in LUT-Based FPGA Technology Mapping , 2006, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
[36] V. Bertacco,et al. Boolean Operations on Decomposed Functions , 2022 .
[37] Yusuke Matsunaga. An Exact and Efficient Algorithms for Disjunctive Decomposition , 1998 .