Channel-drain lateral profile engineering for advanced CMOS on ultra-thin SOI technology

Fully depleted (FD) MOSFETs on SOI substrate have the potential performance required for low-voltage, high-speed applications; however controllability and low drain-source breakdown (BVdss) have been pointed out. In this work, a new transistor channel-drain lateral profile engineering approach is presented and its potential to reduce the short-channel degradation and the parasitic bipolar effect on Vth roll-off and BVdss is experimentally demonstrated in a 0.35-/spl mu/m CMOS on SIMOX process.