Evolution and accomplishments of VLSI yield management at IBM

The methods developed at IBM to manage and improve the yield of some of its newer FET semiconductor products are described. A number of visual inspection and electric monitoring techniques have evolved since discrete semiconductors were manufactured. The data obtained with these techniques are used in self-checking yield models to give the relative yields for all the yield components. The results are applied not only to day-to-day control of the manufacturing lines, but also in the long-range forecasting and planning of future semiconductor integrated circuit products. An example is given comparing the actual and planned yield of a 64K-bit random access memory chip as a function of time. The results show the yield enhancement that was obtained with redundant circuits and additionally with the use of partially functional products. Another example shows the decrease in fault levels over a span of more than ten years.

[1]  R. Smith,et al.  Cost-effective yield improvement in fault-tolerant VLSI memory , 1981, 1981 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

[2]  C. H. Stapper,et al.  Yield Model for Productivity Optimization of VLSI Memory Chips with Redundancy and Partially Good Product , 1980, IBM J. Res. Dev..

[3]  R. M. Warner.  Applying a composite model to the IC yield problem , 1974 .

[4]  P. Sharp,et al.  Redundancy techniques for fast static RAMs , 1981, 1981 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

[5]  R. R. O'Brien,et al.  A Statistical Approach to the Design of Diffused Junction Transistors , 1964, IBM J. Res. Dev..

[6]  R. Cenker,et al.  A fault-tolerant 64K dynamic RAM , 1979, 1979 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

[7]  G. Schwuttke,et al.  Silicon material problems in semiconductor device technology , 1970 .

[8]  C. H. Stapper.  On a composite model to the IC yield problem , 1975 .

[9]  J. Bernard.  The IC yield problem: A tentative analysis for MOS/SOS circuits , 1978, IEEE Transactions on Electron Devices.

[10]  H. J. Geipel,et al.  Reduction of Leakage by Implantation Gettering in VLSI Circuits , 1980, IBM J. Res. Dev..

[11]  R.I. Kung,et al.  An 8Kx8 dynamic RAM with self-refresh , 1982, IEEE Journal of Solid-State Circuits.

[12]  B. T. Murphy,et al.  Cost-size optima of monolithic integrated circuits , 1964 .

[13]  P. Frasch,et al.  Feature size control in IC manufacturing , 1982 .

[14]  T. Masuhara,et al.  HI-CMOSII 4K static RAM , 1981, 1981 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

[15]  O. Paz,et al.  Modification of Poisson statistics: modeling defects induced by diffusion , 1977 .

[16]  S. E. Schuster.  Multiple word/bit line redundancy for semiconductor memories , 1978 .

[17]  J. Sredni.  Use of power transformations to model the yield of IC's as a function of active circuit area , 1975, 1975 International Electron Devices Meeting.

[18]  A. C. Ipri,et al.  Integrated circuit process and design rule evaluation techniques , 1977 .

[19]  R.P. Cenker,et al.  A fault-tolerant 64K dynamic random-access memory , 1979, IEEE Transactions on Electron Devices.

[20]  C. Stapper.  Defect density distribution for LSI yield calculations , 1973 .

[21]  Ching-Lin Jiang,et al.  A 32K static RAM utilizing a three-transistor cell , 1981, 1981 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

[22]  T. Yanagawa.  Yield degradation of integrated circuits due to spot defects , 1972 .

[23]  W. G. Ansley.  Computation of integrated-circuit yields from the distribution of slice yields for the individual devices , 1968 .

[24]  J. K. Ho,et al.  Quality and reliability assurance systems in IBM semiconductor manufacturing , 1982 .

[25]  J. Brady,et al.  A 100ns 64K dynamic RAM using redundancy techniques , 1981, 1981 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

[26]  Robert S. Schwartz,et al.  Solid Logic Technology: Versatile, high-performance microelectronics , 1964, IBM J. Res. Dev..