Reducing switching activity on datapath buses with control-signal gating

This paper presents a technique for saving power dissipation in large datapaths by reducing unnecessary switching activity on buses. The focus of the technique is on achieving effective power savings with minimal overhead. When a bus is not going to be used in a datapath, it is held in a quiescent state by stopping the propagation of switching activity through the module(s) driving the bus. The "observability don't-care condition" of a bus is defined to detect unnecessary switching activity on the bus. This condition is used to gate control signals going to the bus-driver modules so that switching activity on the module inputs does not propagate to the bus. A methodology for automatically synthesizing gated control signals from the register transfer level description of a design is presented. The technique has very low area, delay, power, and designer effort overhead. It was applied to one of the integer execution units of a 64-bit, two-way superscalar RISC microprocessor. Experimental results from running various application programs on the microprocessor show an average of 26.6% reduction in dynamic switching power in the execution unit, with no increase in critical path delay and negligible area overhead.

[1]  Sharad Malik,et al.  Dynamic power management for microprocessors: a case study , 1997, Proceedings Tenth International Conference on VLSI Design.

[2]  Narsingh Deo,et al.  Graph Theory with Applications to Engineering and Computer Science , 1975, Networks.

[3]  Takashi Kambe,et al.  A method of redundant clocking detection and power reduction at RT level design , 1997, Proceedings of 1997 International Symposium on Low Power Electronics and Design.

[4]  Giovanni De Micheli,et al.  Don't care set specifications in combinational and synchronous logic circuits , 1993, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[5]  Thomas D. Burd,et al.  Processor design for portable systems , 1996, J. VLSI Signal Process..

[6]  Luca Benini,et al.  Dynamic power management - design techniques and CAD tools , 1997 .

[7]  M. Sarrafzadeh,et al.  Activity-driven clock design for low power circuits , 1995, Proceedings of IEEE International Conference on Computer Aided Design (ICCAD).

[8]  Frans Theeuwen,et al.  Power Reduction Through Clock Gating by Symbolic Manipulation , 1997 .

[9]  Luca Benini,et al.  Dynamic Power Management , 1998 .

[10]  Sharad Malik,et al.  Guarded evaluation: pushing power management to logic synthesis/design , 1998, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[11]  Massoud Pedram,et al.  Power minimization in IC design: principles and applications , 1996, TODE.

[12]  Vivek Tiwari,et al.  Reducing power in high-performance microprocessors , 1998, Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175).

[13]  Anoop Gupta,et al.  The Stanford FLASH Multiprocessor , 1994, ISCA.

[14]  Hector Sanchez,et al.  A 2.2 W, 80 MHz superscalar RISC microprocessor , 1994 .

[15]  Giovanni De Micheli,et al.  Synthesis and Optimization of Digital Circuits , 1994 .

[16]  Alfred V. Aho,et al.  Data Structures and Algorithms , 1983 .

[17]  Marios C. Papaefthymiou,et al.  Precomputation-based sequential logic optimization for low power , 1994, IEEE Trans. Very Large Scale Integr. Syst..

[18]  Larry L. Biro,et al.  Power considerations in the design of the Alpha 21264 microprocessor , 1998, Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175).