Formal validation of PLC programs: A survey

The aim of this paper is to give an overview of the validation methods for IEC 61131-3 programming languages for programmable logic controllers. More precisely we are focussing on the SFC structuring language and on the LD programming language. The SFC and LD validation methods are detailed after a short presentation of the usual formal methods and of the IEC 61131-3 standard.

[1]  D. J. Holding,et al.  The Formalisation and Analysis of Sequential Function Charts Using a Petri Net Approach , 1996 .

[2]  Itsuo Hatono,et al.  Automatic Generation of Fault Detection Models for Programmable Controller Based Manufacturing Systems Using Complementary-Places Petri Nets , 1996 .

[3]  Edmund M. Clarke,et al.  Formal Methods: State of the Art and Future Directions Working Group Members , 1996 .

[4]  Anders Törne,et al.  Towards Error Recovery in Sequential Control Applications , 1996 .

[5]  Randal E. Bryant,et al.  User experience with high level formal verification (panel) , 1998, DAC.

[6]  Gary J. Powers,et al.  Verification of a logically controlled, solids transport system using symbolic model checking , 1997 .

[7]  Stefan Kowalewski,et al.  Verification of Sequential Controllers with Timing Functions for Chemical Processes , 1996 .

[8]  Ch. André,et al.  Proving Properties of GRAFCET with Synchronous Tools , 1996 .

[9]  Stuart Anderson,et al.  Design for Proof: An Approach to the Design of Domain-Specific Languages , 1998, Formal Aspects of Computing.

[10]  Zhendong Su,et al.  Automatic Analysis of Relay Ladder Logic Programs , 1997 .

[11]  L. Marce,et al.  Synchronous definition of GRAFCET with SIGNAL , 1993, Proceedings of IEEE Systems Man and Cybernetics Conference - SMC.

[12]  Karl-Erik Årzén,et al.  Implementation Aspects of the PLC Standard IEC 1131-3 , 1997 .

[13]  Bruce H. Krogh,et al.  Design recovery for relay ladder logic , 1992, [Proceedings 1992] The First IEEE Conference on Control Applications.

[14]  Wook Hyun Kwon,et al.  Predicting execution time of relay ladder logic for programmable logic controllers , 1996, Proceedings 1996 IEEE Conference on Emerging Technologies and Factory Automation. ETFA '96.

[15]  Thomas A. Henzinger,et al.  Logics and Models of Real Time: A Survey , 1991, REX Workshop.

[16]  I. Moon.  Modeling programmable logic controllers for logic verification , 1994, IEEE Control Systems.

[17]  Jonathan P. Bowen,et al.  Safety-critical systems, formal methods and standards , 1993, Softw. Eng. J..

[18]  P. M. Bruijn,et al.  From Grafcet to Hybrid Automata , 1998 .

[19]  L. Marce,et al.  Two proof methods for the GRAFCET language , 1994 .

[20]  Jonathan S. Ostroff,et al.  Automated Verification of Timed Transition Models , 1989, Automatic Verification Methods for Finite State Systems.

[21]  J. E. Reich,et al.  Symbolic Simulation Based Techniques for Debugging Discrete Control Programs , 1996 .

[22]  Jeannette M. Wing.  A symbiotic relationship between formal methods and security , 1998, Proceedings Computer Security, Dependability, and Assurance: From Needs to Solutions (Cat. No.98EX358).

[23]  G. Villermain-Lecolier,et al.  Abstractions and heuristic for the validation of Grafcet controlled systems , 1997 .

[24]  J.-M. Faure,et al.  Modelling discrete event systems behaviour using the hyperfinite signal , 1997 .

[25]  Jean-Jacques Lesage,et al.  Validation and verification of grafcets using state machine , 1996 .

[26]  Dan Craigen,et al.  An International Survey of Industrial Applications of Formal Methods , 1992, Z User Workshop.

[27]  Zoe Doulgeri,et al.  Validation of a SFC Software Specification by Using Hybrid Automata , 1998 .