Thermal Stress Effects on the Electrical Properties of p-Channel Polycrystalline-Silicon Thin-Film Transistors Fabricated via Metal-Induced Lateral Crystallization

We developed a method to compact the glass sheets of a flat-panel displays that use metal-induced laterally crystallized (MILC) polycrystalline-silicon (poly-Si) thin-film transistors (TFTs), and the effects of thermal stress on the fabricated devices were compared against those of a bare-glass device. The glass substrate was exposed to a temperature of 650 °C for 40 h in order to suppress the glass shrinkage to 0.01 ppm, which suitable for a MILC poly-Si TFT process. The compressive strain that originates from glass shrinkage generally increases the size of the micro-cracks and the vacancies, and as a result, most of the electrical parameters of a bare glass device (such as the on-current, off-current, field-effect mobility, subthreshold slope, and threshold voltage) had a higher level of degradation than those of the device with the compacted glass. The increase in the on-current and the field-effect hole mobility under the compressive strain for poly-Si TFTs showed a similar behavior to that of single-crystalline-silicon (c-Si) TFTs under compressive strain. However, the increase in the off-current was the converse of that of strained c-Si TFT.

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