Delay synchronization loop-based forwarded clocking type receiver

A delay synchronization loop according to the present invention includes a voltage control delay line and a phase detector, the phase detector (100) comprising: a sampler unit (120) for sampling a data signal on the basis of a clock, the sampler unit generating multiple samples having a time interval corresponding to a half of a unit interval; a mode selection unit (130) for selecting a series of samples among the multiple samples generated by the sampler unit (120), a mode selection unit (130) selecting a series of samples starting from an odd-numbered sample or selecting a series of samples starting from an even-numbered sample, according to a mode selection signal; and an XOR unit, in which the series of samples output from the mode selection unit (130) performs an XOR with adjacent samples, for outputting an outcome of the XOR, wherein the output of the XOR unit (140) is used for controlling the voltage control delay line. The present invention can greatly reduce power consumption and an area of the voltage control delay line which consumes a lot of electric power and occupies a chip area.