Speed-independent asynchronous arbiter

A very simple asynchronous arbiter is given for n concurrent asynchronous processors interconnected in a speed-independent way. The arbiter consists of one inverter and n identical modules each incorporating a recently described 2-user arbiter.

[1]  Leonard R. Marino,et al.  The Effect of Asynchronous Inputs on Sequential Network Reliability , 1977, IEEE Transactions on Computers.

[2]  Paolo Corsini.  Asynchronous Interlock Units for Speed-Independent Multiprocessor Systems , 1976, GI Jahrestagung.

[3]  William W. Plummer.  Asynchronous Arbiters , 1972, IEEE Transactions on Computers.

[4]  Warren D. Little,et al.  Asynchronous Arbiter Module , 1975, IEEE Transactions on Computers.