Design of the trigger system for the Auger fluorescence detector

The trigger system for the AUGER fluorescence detector is presented. The main goals of the design were low price, high flexibility of the trigger, high reliability and good testability even at remote operation. The simulation of all boards using VHDL tools resulted in a design which is optimal with respect to these goals and highly independent of existing commercial solutions. The large-scale integration of modern FPGAs yielded a massive parallel system for recognition of tracks and suppression of background. The readout and control is carried out by low cost PCs under the LINUX operating system.