CMOS circuit performance enhancement by surface orientation optimization

With the advent of novel device structures that can be easily fabricated outside of the traditional (100) plane, it may be advantageous to change the crystal orientation to optimize CMOS circuit performance. The use of alternative surface orientations such as [110] and (111) enhances hole mobility while degrading electron mobility, thus allowing for adjustment of the ratio between nMOS and pMOS transistor drive currents. By optimizing the surface orientation, up to a 15% improvement in gate delay can be expected. This value depends upon the type of logic gate, the off-state leakage specification, and technology scaling trends. The introduction of high-/spl kappa/ dielectrics may provide an added incentive for the use of non-(100) orientations as this method of circuit performance enhancement may be used to compensate for mobility degradation from the high-/spl kappa/ interface. Additional concerns including layout area and device reliability are discussed.

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