On the use of linear sums in exhaustive testing

The increasing role of exhaustive testing techniques in VLSI has prompted a number of investigations into methods for achieving locally exhaustive testing of the components of a large digital circuit using a comparatively small number of test signals. This paper examines the possibility of introducing linear sums of the test signals into this testing process. It is shown that with the addition of a relatively small amount of additional circuitry, significant reductions in the number of required test signals (and tests) can often be achieved. In particular, it is shown that for any specific combinational circuit the number of required test signals can be made to be independent of the number of inputs and to depend only logarithmically on the number of outputs. The role of these linear sums in the generation of universal test sets is also discussed.