Test Scheduling for Network-on-Chip Using XY-Direction Connected Subgraph Partition and Multiple Test Clocks

It is attractive to reuse the on-chip functional interconnects as test access mechanism (TAM) in network-on-chip (NoC) system testing. However, in the methodology of NoC-reuse as TAM, the influence factors in NoC testing significantly increased. To further reduce test time and show significant gains over other work, we propose XY-direction connected subgraph partition (XYCSP) approach to eliminate the path conflicts before testing, and concurrently determine the position of test access points. We then present a multiple test clock strategy to bridge the gap between the NoC channel bandwidth and the core test wrapper bandwidth. With the help of adaptive probability gate quantum-inspired evolutionary algorithm (APGQEA) strategy, which blends adaptive strategy and multi-nary oriented techniques, the proposed NoC test scheduling algorithm permits quick exploration and exploitation of the solution space. Moreover, power constraints are also taken into account. Experimental results for the ITC’02 benchmarks show that the proposed scheme can achieve shorter test time compared to prior works.

[1]  Yuncai Liu,et al.  Probability evolutionary algorithm for functional and combinatorial optimization , 2008, 2008 7th World Congress on Intelligent Control and Automation.

[2]  Alexandre M. Amory,et al.  A new test scheduling algorithm based on Networks-on-Chip as Test Access Mechanisms , 2011, J. Parallel Distributed Comput..

[3]  Abderezak Touzene,et al.  On All-to-All Broadcast in Dense Gaussian Network On-Chip , 2015, IEEE Transactions on Parallel and Distributed Systems.

[4]  Haidar M. Harmanani,et al.  Thermal-aware test scheduling using network-on-chip under multiple clock rates , 2013 .

[5]  Fernando Gehm Moraes,et al.  MoNoC: A monitored network on chip with path adaptation mechanism , 2014, J. Syst. Archit..

[6]  Luigi Carro,et al.  Reusing an on-chip network for the test of core-based systems , 2004, TODE.

[7]  Ming Li,et al.  An efficient wrapper scan chain configuration method for network-on-chip testing , 2006, IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures (ISVLSI'06).

[8]  Rabi N. Mahapatra,et al.  A TDM Test Scheduling Method for Network-on-Chip Systems , 2005, 2005 Sixth International Workshop on Microprocessor Test and Verification.

[9]  Chouki Aktouf,et al.  A complete strategy for testing an on-chip multiprocessor architecture , 2002, IEEE Design & Test of Computers.

[10]  Krishnendu Chakrabarty,et al.  Accepted for Publication in Ieee Transactions on Computer-aided Design of Integrated Circuits and Systems Test Scheduling for Core-based Systems Using Mixed-integer Linear Programming , 2000 .

[11]  Chunsheng Liu,et al.  Test scheduling with thermal optimization for network-on-chip systems using variable-rate on-chip clocking , 2006, Proceedings of the Design Automation & Test in Europe Conference.

[12]  Alexandre M. Amory,et al.  Wrapper design for the reuse of a bus, network-on-chip, or other functional interconnect as test access mechanism , 2007, IET Comput. Digit. Tech..

[13]  Krishnendu Chakrabarty,et al.  Optimization of Test Pin-Count, Test Scheduling, and Test Access for NoC-Based Multicore SoCs , 2014, IEEE Transactions on Computers.

[14]  Ge-Ming Chiu,et al.  An Efficient Submesh Allocation Scheme for Two-Dimensional Meshes with Little Overhead , 1999, IEEE Trans. Parallel Distributed Syst..

[15]  Kees G. W. Goossens,et al.  Bringing communication networks on a chip: test and verification implications , 2003, IEEE Commun. Mag..

[16]  Jong-Hwan Kim,et al.  Quantum-inspired evolutionary algorithms with a new termination criterion, H/sub /spl epsi// gate, and two-phase scheme , 2004, IEEE Transactions on Evolutionary Computation.

[17]  Irith Pomeranz,et al.  SOC test scheduling using simulated annealing , 2003, Proceedings. 21st VLSI Test Symposium, 2003..

[18]  Ye Zhang,et al.  Cost-Effective Power-Aware Core Testing in NoCs Based on a New Unicast-Based Multicast Scheme , 2011, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[19]  Hideo Fujiwara,et al.  Multicast-Based Testing and Thermal-Aware Test Scheduling for 3D ICs with a Stacked Network-on-Chip , 2016, IEEE Transactions on Computers.

[20]  Gexiang Zhang,et al.  Quantum-inspired evolutionary algorithms: a survey and empirical study , 2011, J. Heuristics.

[21]  Luigi Carro,et al.  The impact of NoC reuse on the testing of core-based systems , 2003, Proceedings. 21st VLSI Test Symposium, 2003..

[22]  한국현,et al.  Quantum-inspired evolutionary algorithm = 양자 개념을 도입한 진화 알고리즘 , 2003 .

[23]  Tony Hey,et al.  Quantum computing: an introduction , 1999 .

[24]  Andrew B. Kahng,et al.  ORION 2.0: A Power-Area Simulator for Interconnection Networks , 2012, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[25]  Jong-Hwan Kim,et al.  On setting the parameters of quantum-inspired evolutionary algorithm for practical application , 2003, The 2003 Congress on Evolutionary Computation, 2003. CEC '03..

[26]  Krishnendu Chakrabarty,et al.  Test-Delivery Optimization in Manycore SOCs , 2014, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[27]  Sungju Park,et al.  Hybrid Test Data Transportation Scheme for Advanced NoC-Based SoCs , 2015 .

[28]  Érika F. Cota,et al.  Constraint-Driven Test Scheduling for NoC-Based Systems , 2006, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[29]  Chellapilla Patvardhan,et al.  Quantum-Inspired Evolutionary Algorithm for difficult knapsack problems , 2015, Memetic Comput..

[30]  Cheng-Wen Wu,et al.  A Graph-Based Approach to Power-Constrained SOC Test Scheduling , 2004, J. Electron. Test..

[31]  Fawnizu Azmadi Hussin,et al.  Optimization of NoC Wrapper Design under Bandwidth and Test Time Constraints , 2007, 12th IEEE European Test Symposium (ETS'07).

[32]  Giovanni De Micheli,et al.  Design, synthesis, and test of networks on chips , 2005, IEEE Design & Test of Computers.

[33]  Sungju Park,et al.  Parallel test method for NoC-based SoCs , 2009, 2009 International SoC Design Conference (ISOCC).

[34]  Julien Pouget,et al.  SOC test time minimization under multiple constraints , 2003, 2003 Test Symposium.

[35]  Krishnendu Chakrabarty,et al.  System-on-a-chip test scheduling with precedence relationships, preemption, and power constraints , 2002, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[36]  Érika F. Cota,et al.  Power-aware test scheduling in network-on-chip using variable-rate on-chip clocking , 2005, 23rd IEEE VLSI Test Symposium (VTS'05).

[37]  Santanu Chattopadhyay,et al.  Genetic algorithm based test scheduling and test access mechanism design for system-on-chips , 2003, 16th International Conference on VLSI Design, 2003. Proceedings..

[38]  Michael Defoin-Platel,et al.  Quantum-Inspired Evolutionary Algorithm: A Multimodel EDA , 2009, IEEE Transactions on Evolutionary Computation.

[39]  Luigi Carro,et al.  Power-aware noc reuse on the testing of core-based systems , 2003, International Test Conference, 2003. Proceedings. ITC 2003..

[40]  Jin HoAhn,et al.  Test Scheduling of NoC-Based SoCs Using Multiple Test Clocks , 2006 .

[41]  Jong-Hwan Kim,et al.  Quantum-inspired evolutionary algorithm for a class of combinatorial optimization , 2002, IEEE Trans. Evol. Comput..

[42]  Erik Jan Marinissen,et al.  A set of benchmarks for modular testing of SOCs , 2002, Proceedings. International Test Conference.

[43]  Erik Jan Marinissen,et al.  Test Wrapper and Test Access Mechanism Co-Optimization for System-on-Chip , 2002, J. Electron. Test..