Design and Implementation of FPGA-Based Modified BKNN Classifier

Artificial Neural Network (ANN) is an important tool for Pattern Recognition in Artificial Intelligence field. In this paper, we presented a hardware implementation of ANN based on modification of Boolean k-nearest neighbor (BKNN) classifier proposed by Gazula and Kabuka. BKNN is a kind of supervised classifier using Boolean Neural Network, which has binary inputs and outputs, integer weights, fast learning and classification, and guaranteed convergence. The emphasis of this design is that it is implemented on Field Programming Gate Array (FPGA) chip through Verilog HDL codes programming so that the classifier can be more convenient to be carried and reconfigurable. The satisfying experimental results demonstrate that the modified version of BKNN is characteristic with fast, robust classification ability. It offers the Artificial Intelligence a significant tool in both computer vision and pattern recognition.

[1]  Mansur R. Kabuka,et al.  Neural network transformation of arbitrary Boolean functions , 1992, Optics & Photonics.

[2]  S. Bhide,et al.  A real-time solution for the traveling salesman problem using a Boolean neural network , 1993, IEEE International Conference on Neural Networks.

[3]  Mansur R. Kabuka,et al.  A Novel Feature Recognition Neural Network and its Application to Character Recognition , 1994, IEEE Trans. Pattern Anal. Mach. Intell..

[4]  Mansur R. Kabuka,et al.  Design of Supervised Classifiers Using Boolean Neural Networks , 1995, IEEE Trans. Pattern Anal. Mach. Intell..

[5]  Xiaohong Li,et al.  Labeling of MR brain images using Boolean neural network , 1996, IEEE Trans. Medical Imaging.

[6]  Guy Smith.  Comments on 'Design of Supervised Classifiers Using Boolean Neural Neworks' , 1999, IEEE Trans. Pattern Anal. Mach. Intell..

[7]  Zhou Lin.  A writer identification of text-Independent based on feed-forward neural betworks , 2002 .

[8]  Hiroomi Hikawa,et al.  A digital hardware pulse-mode neuron with piecewise linear activation function , 2003, IEEE Trans. Neural Networks.

[9]  Hiroomi Hikawa.  A multilayer neural network with pulse position modulation , 2003, Systems and Computers in Japan.

[10]  D D Earl,et al.  Development of an FPGA-Based Hardware Evaluation System for Use with GA-Designed Artificial Neural Networks , 2004 .

[11]  Jihong Liu,et al.  A Survey of FPGA-Based Hardware Implementation of ANNs , 2005, 2005 International Conference on Neural Networks and Brain.