EVAS: a new evolution algorithm solving the assignment problem in analog layout with automatic consideration of matching constraints

In this paper a new evolution approach for solving the assignment problem on analog transistor arrays is presented. Several constraints given in analog layout are considered. This approach exploits circuit symmetries to improve the resulting layout. The required symmetry informations are efficiently extracted by applying the new algorithm SYMALYS to the original circuit description. The generally applicable algorithm SYMALYS is described. In order to utilize the detected symmetries, a problem-specific suitable cost-function is employed. Furthermore some simplifications useful for application on transistor arrays are employed for benefit of faster computation. The implemented algorithm EVAS has been tested with industrial examples and the result is given.