CGTA: current gain-based timing analysis for logic cells
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[1] Y. Yamada,et al. Equivalent waveform propagation for static timing analysis , 2004, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
[2] Ken Tseng,et al. A robust cell-level crosstalk delay change analysis , 2004, IEEE/ACM International Conference on Computer Aided Design, 2004. ICCAD-2004..
[3] Alexander Korshak,et al. An effective current source cell model for VDSM delay calculation , 2001, Proceedings of the IEEE 2001. 2nd International Symposium on Quality Electronic Design.
[4] Martin D. F. Wong,et al. Blade and razor: cell and interconnect delay analysis using current-based models , 2003, Proceedings 2003. Design Automation Conference (IEEE Cat. No.03CH37451).
[5] Lawrence T. Pileggi,et al. Modeling the "Effective capacitance" for the RC interconnect of CMOS gates , 1994, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[6] Shahin Nazarian,et al. Sensitivity-based gate delay propagation in static timing analysis , 2005, Sixth international symposium on quality electronic design (isqed'05).
[7] David Blaauw,et al. An effective capacitance based driver output model for on-chip RLC interconnects , 2003, Proceedings 2003. Design Automation Conference (IEEE Cat. No.03CH37451).