The efficient mCBE algorithm and quantization numbers for multiplierless and low complexity DCT/IDCT Image Compression Architecture

This paper presents a multiplierless and low complexity of DCT/IDCT Image Compression Architecture by using two approaches. First, we propose multiplication decomposition by using our algorithm. This algorithm minimizes shifter-adder components to substitute multiplier efficiently. We named it as multiplication from Common Binary Expression (mCBE) Algorithm. Second, we propose alternative quantization numbers which can be simply implemented as shifter in digital hardware. These numbers can also retain good quality of compressed image compared to JPEG recommendation numbers. We named them as FathQuantz Numbers. Those improvements lead our proposed architecture becomes multiplierless and low complexity. The result states that our proposed 8-points 1D-DCT design has only 6 stages and 8-points 1D-IDCT design has only 7 stages. Here, we define 1 stage is equal to shifter or 2-inputs adder delay. So, by pipelining method, we can achieve high speed architecture with latency as trade off consideration. This design has been synthesized and it can speed up to 1.41ns crithical path delay (709.22MHz).