Adaptive Voltage Scaling by In-situ Delay Monitoring

In the Pre-Error AVS scheme the timing information is provided by in-situ delay monitors (Pre-Error flip-flops), that detect late but still non-erroneous data transitions in critical paths. Late data transitions are defined by the pre-error detection window, i.e. a defined time interval T pre before the triggering edge of the clock.

[1]  Doris Schmitt-Landsiedel,et al.  A variation-aware adaptive voltage scaling technique based on in-situ delay monitoring , 2011, 14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems.

[2]  Gabriel A. Rincon-Mora,et al.  A low-voltage, low quiescent current, low drop-out regulator , 1998, IEEE J. Solid State Circuits.

[3]  Doris Schmitt-Landsiedel,et al.  An energy-efficient supply voltage scheme using in-situ Pre-Error detection for on-the-fly voltage adaptation to PVT variations , 2011, 2011 International Symposium on Integrated Circuits.

[4]  D. Schmitt-Landsiedel,et al.  A fully-integrated system power aware LDO for energy harvesting applications , 2011, 2011 Symposium on VLSI Circuits - Digest of Technical Papers.

[5]  Doris Schmitt-Landsiedel,et al.  Adaptive voltage scaling by in-situ delay monitoring for an image processing circuit , 2012, 2012 IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS).