Characterization and modeling of intradie variation and its applications to design for manufacturability

Device scaling increases the impact of within-die variation or mismatch on the performance and yield of many important components of System on Chip (SoC) designs. This has created a need for accurate characterization, modeling, and simulation of mismatch. This paper provides a brief overview of the recent progress in these areas along with an example illustrating the application of these techniques to Design for Manufacturability (DFM) of Ultra Deep Submicron (UDSM) technologies.