Distribution fitting approach to application fitness assessment

On top of assessing the specification compliance, it is also important to verify the behavior and performance of the electronic components in the targeted application. This is usually achieved by jointly simulating the component and the application. There is a particular interest in finding the application yield caused by the process variation of the electronic component. The cost of the experiments is usually high, and, if the estimation of the Failure Probability (FP) is done from counts of failure from few simulations, then, the FP is not very accurate. We propose a method of FP estimation based on distribution fitness which represents a more robust statistic. The validation of the method is made on an E-Bike use case and the results show that the proposed approach is more accurate than the one based on counts. The investigation is made by taking into account the role of the operating conditions in the experiments. We achieve this by grouping the test scenarios under a number of mission profiles, on which the developed methods are carried out.

[1]  Xin Chen,et al.  From statistical model checking to statistical model inference: Characterizing the effect of process variations in analog circuits , 2013, 2013 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

[2]  Iliycho Petkov Iliev,et al.  Application of the Classification and Regression Trees for Modeling the Laser Output Power of a Copper Bromide Vapor Laser , 2013 .

[3]  Xuan Fan Intelligent Power Assist Algorithms for Electric Bicycles , 2010 .

[4]  Lawrence T. Pileggi,et al.  Efficient Parametric Yield Extraction for Multiple Correlated Non-Normal Performance Distributions of Analog/RF Circuits , 2007, 2007 44th ACM/IEEE Design Automation Conference.

[5]  J. Beck,et al.  Estimation of Small Failure Probabilities in High Dimensions by Subset Simulation , 2001 .

[6]  Andi Buzo,et al.  Integrated circuits' characterization for non-normal data in semiconductor quality analysis , 2017, 2017 22nd IEEE European Test Symposium (ETS).

[7]  Francky Catthoor,et al.  Yield prediction for architecture exploration in nanometer technology nodes:: a model and case study for memory organizations , 2006, Proceedings of the 4th International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS '06).

[8]  Peter Feldmann,et al.  Statistical integrated circuit design , 1993 .

[9]  Rob A. Rutenbar,et al.  Generation of yield-aware Pareto surfaces for hierarchical circuit design space exploration , 2006, 2006 43rd ACM/IEEE Design Automation Conference.

[10]  Petru Eles,et al.  Probabilistic Analysis of Power and Temperature Under Process Variation for Electronic System Design , 2014, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.