Stack distance based worst-case instruction cache performance analysis

The worst-case execution time (WCET) analysis is critical to ensure the schedulability and correctness of hard real-time systems. Modern microprocessors, however, make the WCET analysis complicated, mainly because of their performance acceleration features like caches, pipelines, out-of-order execution, etc. This paper focuses on studying an accurate static timing analysis approach for instruction caches with the LRU-based strategy by computing the worst-case stack distance. The experimental results indicate that our approach can accurately predict worst-case instruction cache performance. Also, the stack distance based timing analysis approach can efficiently categorize worst-case instruction cache misses into cold, conflict and capacity misses, which can provide useful insights to improve the worst-case instruction cache performance.