A time-spreading calibration technique for multi-bit/stage pipeline ADCs

This paper describes a robust and effective calibration algorithm for pipelined analog-to-digital converters, which compensates for large gain errors, without the requirement for a long startup time as required by the other dither-based algorithms presented in literature. The proposed technique, timespreading self-calibration, operates the front-end sample-andhold stage in half rate at startup and cancels out the strong input-interference by using subtractive correlation, achieves a quick convergence. When the sample-and-hold stage operates in full rate as normal, the algorithm works as a background dither-based scheme and enables to calibrate time-variant gain errors. Simulation results show that it only needs wake-up time of 3 × 10 5 ·T s to correct a 15-bit pipelined ADC in the presence of realistic capacitor mismatch and finite op-amp gain, where T s is the sampling period.