In the modern era of CPU complexity advancements, Processor verification has always been an ever-increasing challenge. The gap between what a verification plan can offer nowadays and the current technology requirements is constantly widened. Despite many efforts on perfecting “Golden-verification-models” during the design phase, and adoption of object-oriented programming into the whole process; many industry experts still consider solo verification test benches as an extreme, time-consuming barricade that leads to a longer time-to-market and a questionable continuity of the current verification process. The Universal Verification Methodology (UVM), came in action as a literal savior to the whole verification community, by offering a merge between System Verilog and SystemC into one environment that is completely standardized, constrained, and reusable, allowing a powerful verification methodology to a wide range of design sizes and types. The main contribution that this project introduces is implementing a generic UVM, in other words, building one verification environment that can be used to accommodate many RTL designs (Soft Processors), having not only different Instruction Set Architectures (ISAs) -of the same categories-, but also different techniques/mechanisms handling the pipeline infrastructures. The proposed generic UVM (GUVM) structure permits the targeted user to attach any soft processor (core) having nearly the same micro-architecture to our test bench, and monitor both: CPU internal behavior and the complete flow of all supported instructions.
[1]
Hassan Mostafa,et al.
Development of a Generic and a Reconfigurable UVM-Based Verification Environment for SoC Buses
,
2019,
2019 31st International Conference on Microelectronics (ICM).
[2]
Ahmed Shalaby,et al.
Fast Reliable Verification Methodology for RISC-V Without a Reference Model
,
2018,
2018 19th International Workshop on Microprocessor and SOC Test and Verification (MTV).
[3]
Hassan Mostafa,et al.
Constructing Effective UVM Testbench for DRAM Memory Controllers
,
2018,
2018 New Generation of CAS (NGCAS).
[4]
Khaled Salah,et al.
A Unified UVM Architecture for Flash-Based Memory
,
2017,
2017 18th International Workshop on Microprocessor and SOC Test and Verification (MTV).
[5]
Andrew Waterman,et al.
The RISC-V Reader: An Open Architecture Atlas
,
2017
.
[6]
A. Fiergolski.
Simulation environment based on the Universal Verification Methodology
,
2017
.
[7]
Ray Salemi,et al.
The UVM Primer: A Step-by-Step Introduction to the Universal Verification Methodology
,
2013
.
[8]
Michael Gautschi,et al.
KISS PULPino - Updates on PULPino
,
2016
.
[9]
Mustafa Khairallah.
Reusable Processor Verification Methodology Based on UVM
,
2014
.