Comparative Analysis of Array Multiplier Using Different Logic Styles

Multiplier is one of the most important arithmetic unit in Microprocessors and DSPs and also a major source of power dissipation. Reducing the power dissipation of multipliers is a key to satisfy the overall power budget of various digital circuits and systems. this paper elaborates the array multiplier through different logic styles. The fundamental units to design a multiplier are adders. The various types of adders used in this paper are complementary MOS (CMOS) logic style, complementary pass- transistor (CPL) logic style, double-pass transistor (DPL) logic style and domino logic style. The main objective of our work is to calculate the average power, delay and PDP of 4x4 multipliers. The design of full adder for low power is obtained and the low power units are implemented on the array multiplier and the results are analyzed for better performance. The designs are done using TANNER S-EDIT tool and are simulated using T-SPICE. The multiplier architectures are designed using the three better above said full adders and the results are compared so that we can obtain a better multiplier design.

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