We have fully integrated a 64 Kb MRAM with 0.24 /spl mu/m-CMOS technology. A new sensing scheme employing a separated half-current source is adopted for the reference bit line to increase the sensing signal. To reduce cell resistance, a Co salicidation process is applied to transistor formation. In key fabrication processes, the roughness of the buffer layer, on which the MTJs are stacked, is reduced by using Ru on the TiN bottom electrode, and magnetic disturbance is avoided by depositing TiN hard masks on the MTJ under low-power and low-temperature conditions. The tunneling barrier micro-bridge due to the attachment of by-products during etching is completely eliminated by adopting a 2-step MTJ etch with an introduced capping oxide layer. Consequently, MR values of >30% are found in more than 90% of chips.