An Agile and Low Cost FPGA Implementation of MPEG-2 TS Remultiplexer for CATV Head-End Equipment

As the progress of technology, the application of field programmable gate array (FPGA) becomes more prevailing and flexible. Especially, the reiterated configuration features are further adopted to system level integration. This paper proposes a low-cost FPGA implementation of the MPEG-2 transport stream (TS) remultiplexer in a cable television (CATV) head-end equipment. Predominant functions on the FPGA include a unified interface for input, program clock reference (PCR) corrector, and rate controller. Due to FPGA’s facile cloning defect, we also propose a security mechanism to protect our intellectual property in prevention of piracy. The whole system consists of a central processing unit (CPU), FPGA, complex programmable logic device (CPLD), quadrature amplitude modulation (QAM) modulator integrated circuit (IC), ASI deserializer IC and QAM receiver IC. Meanwhile, most of the related experimental verification evidences are also disclosed.