Exhaustive simulation need not require an exponential number of tests
暂无分享,去创建一个
[1] Randal E. Bryant,et al. Formal verification of memory circuits by switch-level simulation , 1991, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[2] Robert K. Brayton,et al. Reduced offsets for minimization of binary-valued functions , 1991, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[3] Randal E. Bryant,et al. Graph-Based Algorithms for Boolean Function Manipulation , 1986, IEEE Transactions on Computers.
[4] Kenneth J. Supowit,et al. A New Method for Verifying Sequential Circuits , 1986, DAC 1986.
[5] David A. Basin,et al. Verification Of Combinational Logic in Nuprl , 1989, Hardware Specification, Verification and Synthesis.
[6] Randal E. Bryant,et al. A methodology for hardware verification based on logic simulation , 1987, JACM.
[7] Daniel L. Ostapko,et al. MINI: A Heuristic Approach for Logic Minimization , 1974, IBM J. Res. Dev..
[8] Alberto L. Sangiovanni-Vincentelli,et al. PROTEUS : A Logic Verification System for Combinational Circuits , 1986, ITC.
[9] Srinivas Devadas,et al. On the verification of sequential machines at differing levels of abstraction , 1988, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[10] A. Richard Newton,et al. An efficient verifier for finite state machines , 1991, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[11] Michael L. Bushnell,et al. EST: The new frontier in automatic test-pattern generation , 1990, DAC '90.
[12] Vijay Pitchumani,et al. A formal method for computer design verification , 1982, DAC 1982.
[13] Robert K. Brayton,et al. Logic Minimization Algorithms for VLSI Synthesis , 1984, The Kluwer International Series in Engineering and Computer Science.
[14] Rodolfo Betancourt. Derivation of Minimum Test Sets for Unate Logical Circuits , 1971, IEEE Transactions on Computers.