FPGA implementation and experimental evaluation of a multizone network cache

Abstract Network routers rely on content addressable memories (CAMs) to accelerate the process of looking up the next hop of a packet. The input for this lookup is the destination address of the packet. This article describes our implementation and evaluation of a versatile prototype for a CAM. This prototype allows the empirical evaluation of the idea of caching lookup results in a multizone cache organized according to the length of the network prefix portion of the addresses. Implementing a cache in an FPGA efficiently required the design of a new cache replacement policy, the Bank N th Chance policy. In this article we present results from a functional simulator that allows the comparison of this new policy with existing ones such as least recently used, first in, first out and Second Chance. With a complete and functional prototype in a Xilinx Virtex 2000E device, we also report frequency of operation and occupation of the device. We present programmable logic design techniques that enable the implementation of ternary logic CAM cells, the efficient implementation of the new policy reference fields, and the pipelining of lookups.