Nexus: an asynchronous crossbar interconnect for synchronous system-on-chip designs
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[1] Kenneth S. Stevens,et al. Energy and performance models for clocked and asynchronous communication , 2003, Ninth International Symposium on Asynchronous Circuits and Systems, 2003. Proceedings..
[2] Mark R. Greenstreet,et al. Efficient self-timed interfaces for crossing clock domains , 2003, Ninth International Symposium on Asynchronous Circuits and Systems, 2003. Proceedings..
[3] Alain J. Martin. The limitations to delay-insensitivity in asynchronous circuits , 1990 .
[4] Andrew M Lines,et al. Pipelined Asynchronous Circuits , 1998 .
[5] Peter Robinson,et al. Point to point GALS interconnect , 2002, Proceedings Eighth International Symposium on Asynchronous Circuits and Systems.
[6] Paul I. Pénzes,et al. The design of an asynchronous MIPS R3000 microprocessor , 1997, Proceedings Seventeenth Conference on Advanced Research in VLSI.
[7] William John Bainbridge,et al. Delay insensitive system-on-chip interconnect using 1-of-4 data encoding , 2001, Proceedings Seventh International Symposium on Asynchronous Circuits and Systems. ASYNC 2001.