Device package substrate and manufacturing method of the same

According to one embodiment of the invention, the second wiring layer is separated from the first wiring layer and the first wiring substrate on which the cavity comprises a chip mounting area on the top surface is formed, formed to extend into the cavity formed, located on the chip mounting area and said first wiring layer and is formed so as to cover the chip, the first wiring, the second wiring layer and the chip is connected to the second wiring layer, insulating layer and the outer element having a contact hole exposing a portion of the second wiring layer to connect the device package, the substrate including the bump pad formed on the contact hole, and provides a method of manufacturing the same. According to the invention, can be implemented by a device package substrate, the chip is received in the cavity provides a device package substrate, and a method of manufacture that can manufacturing process is simple, reduces the overall system size than the conventional device. The semiconductor package chip, cavity