14nm FinFET device electronic study

In this paper, wafers with (100) substrate and standard notch orientation were used. Our results showed that the mobility for FinFET PMOS device is almost 2 times higher than for the planar device, mainly due to the benefit from the (110) sidewalls channel. The CV curve showed the good quality of the gate dielectric. DIBL is 24mv/v and 72mv/decade for the swing for the short channel device at Vdd=0.8V. For PMOS devices without any stress engineering, normalizing the electrical parameters to the actual fin perimeter, we observed that the PMOS short channel device universal curve is 35% below the 14nm technology target but almost meets the expectation of devices without S/D epitaxial stress engineering and contact resistance optimization. The device performance and short channel effect behavior represent FinFET device advantages. The process optimization and embedded source/drain stress engineering implementation would further booster the FinFET device performance.