Comparative Study of Single, Regular and Flip Well Subthreshold SRAMs in 22 nm FDSOI Technology

This study presents a comparative study of single, regular and flip well subthreshold SRAMs in 22 nm FDSOI technology. A 7T loadless SRAM cell with a decoupled read and write port has been used as a case study. Simulation results, based on the extracted netlist from layout, show that the speed of the flip well SRAM is significantly better than that of the single and regular well SRAMs. In terms of leakage current, single well is the best option. The regular well type has lower static noise margin (SNM) variability. Among all devices used (HVT, RVT, LVT and, SLVT) available in a commercially available 22 nm FDSOI technology, the best combination for minimizing energy per access is HVT devices as driver transistors and RVT for the rest of the transistors. This study may help designers to select an optimal architecture based on their application and performance requirements. The 22 nm FDSOI technology enables a wide range of back gate bias voltages to improve the read stability and write ability of the SRAMs and, hence, their minimum operating voltage and power consumption.

[1]  Antonio Petraglia,et al.  Static noise margin trade-offs for 6T-SRAM cell sizing in 28 nm UTBB FD-SOI CMOS technology , 2018, Microelectron. J..

[2]  Meng-Fan Chang,et al.  A 130 mV SRAM With Expanded Write and Read Margins for Subthreshold Applications , 2011, IEEE Journal of Solid-State Circuits.

[3]  David Blaauw,et al.  Analysis and mitigation of variability in subthreshold design , 2005, ISLPED '05. Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005..

[4]  Jason Liu,et al.  A High-Density Subthreshold SRAM with Data-Independent Bitline Leakage and Virtual Ground Replica Scheme , 2007, 2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

[5]  H. Shimizu,et al.  A 1.4 ns access 700 MHz 288 kb SRAM macro with expandable architecture , 1999, 1999 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC. First Edition (Cat. No.99CH36278).

[6]  T. Skotnicki,et al.  Innovative Materials, Devices, and CMOS Technologies for Low-Power Mobile Multimedia , 2008, IEEE Transactions on Electron Devices.

[7]  K.Y. Lee,et al.  A 0.18 /spl mu/m CMOS logic technology with dual gate oxide and low-k interconnect for high-performance and low-power applications , 1999, 1999 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.99CH36325).

[8]  A.P. Chandrakasan,et al.  A 256 kb 65 nm 8T Subthreshold SRAM Employing Sense-Amplifier Redundancy , 2008, IEEE Journal of Solid-State Circuits.

[9]  A. Chandrakasan,et al.  A 180mV FFT processor using subthreshold circuit techniques , 2004, 2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519).

[10]  Anantha Chandrakasan,et al.  A 0.36V 128Kb 6T SRAM with energy-efficient dynamic body-biasing and output data prediction in 28nm FDSOI , 2016, ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference.

[11]  Sani R. Nassif,et al.  High Performance CMOS Variability in the 65nm Regime and Beyond , 2006, 2007 IEEE International Electron Devices Meeting.

[12]  David Blaauw,et al.  A reconfigurable sense amplifier with 3X offset reduction in 28nm FDSOI CMOS , 2015, 2015 Symposium on VLSI Circuits (VLSI Circuits).

[13]  Ali Sheikholeslami,et al.  Cross-coupled bit-line biasing for 22-nm SRAM , 2009, 2009 Ph.D. Research in Microelectronics and Electronics.

[14]  T. Iwasaki,et al.  A 16 Mb 400 MHz loadless CMOS four-transistor SRAM macro , 2000, 2000 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.00CH37056).

[15]  A. Chandrakasan,et al.  A 256kb Sub-threshold SRAM in 65nm CMOS , 2006, 2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers.

[16]  Jun Zhou,et al.  SRAM devices and circuits optimization toward energy efficiency in multi-Vth CMOS , 2015, Microelectron. J..

[17]  E. Seevinck,et al.  Static-noise margin analysis of MOS SRAM cells , 1987 .

[18]  C.H. Kim,et al.  A 0.2 V, 480 kb Subthreshold SRAM With 1 k Cells Per Bitline for Ultra-Low-Voltage Computing , 2008, IEEE Journal of Solid-State Circuits.

[19]  Anantha Chandrakasan,et al.  A 28nm high-density 6T SRAM with optimized peripheral-assist circuits for operation down to 0.6V , 2011, 2011 IEEE International Solid-State Circuits Conference.

[20]  Joseph Wang,et al.  A dual core oxide 8T SRAM cell with low Vccmin and dual voltage supplies in 45nm triple gate oxide and multi Vt CMOS for very high performance yet low leakage mobile SoC applications , 2010, 2010 Symposium on VLSI Technology.

[21]  K. Nii,et al.  A 28-nm dual-port SRAM macro with active bitline equalizing circuitry against write disturb issue , 2010, 2010 Symposium on VLSI Circuits.

[22]  Tsutomu Yoshihara,et al.  A new 7-transistor SRAM cell design with high read stability , 2010, 2010 International Conference on Electronic Devices, Systems and Applications.

[23]  Kenichi Osada,et al.  Universal-Vdd 0.65-2.0-V 32-kB cache using a voltage-adapted timing-generation scheme and a lithographically symmetrical cell , 2001, IEEE J. Solid State Circuits.

[24]  Trond Ytterdal,et al.  A loadless 6T SRAM cell for sub- & near- threshold operation implemented in 28 nm FD-SOI CMOS technology , 2018, Integr..