Asymmetric Dual-Spacer Trigate FinFET Device-Circuit Codesign and Its Variability Analysis

High-k spacer materials have been extensively studied nowadays for the enhancement of electrostatic control and suppression of short-channel effects in nanoscaled devices. However, the exorbitant increase in fringe capacitance due to high-k spacers deteriorates the dynamic circuit performance. Interestingly, this paper demonstrates effective reduction in circuit delay with an optimum usage of high-k spacer material. An asymmetric dual-k spacer trigate (ADS-TG) FinFET architecture is employed for the purpose. From extensive 3-D simulations, it is demonstrated that ADS-TG device significantly improves the overall circuit delay and robustness performance while fully capturing the fringe capacitance effects. A FinFET inverter and a three-stage ring oscillator (RO3) are adopted to investigate the performances carefully. In comparison with the conventional device, the ADS-TG device speeds up the RO3 circuit by 22.6% and 32.4% using high-k spacer dielectrics HfO2 and TiO2, respectively. Contradictorily, a purely high-k FinFET device deteriorates the RO3 delay per stage up to 11%. Furthermore, the effects of supply voltage and underlap length on ADS-TG-based RO3 delay over the conventional ones are also dealt in. The ADS-TG device and static RAM based on this device prove to be more variation tolerant in comparison with the conventional configurations.

[1]  Nobuyuki Sano,et al.  On discrete random dopant modeling in drift-diffusion simulations: physical meaning of 'atomistic' dopants , 2002, Microelectron. Reliab..

[2]  K. Roy,et al.  Asymmetric Drain Spacer Extension (ADSE) FinFETs for Low-Power and Robust SRAMs , 2011, IEEE Transactions on Electron Devices.

[3]  F. Moradi,et al.  Asymmetrically Doped FinFETs for Low-Power Robust SRAMs , 2011, IEEE Transactions on Electron Devices.

[4]  Niraj K. Jha,et al.  Parasitics-Aware Design of Symmetric and Asymmetric Gate-Workfunction FinFET SRAMs , 2014, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[5]  Brajesh Kumar Kaushik,et al.  Design Metrics Improvement for SRAMs Using Symmetric Dual- $k$ Spacer (SymD-$k$) FinFETs , 2014, IEEE Transactions on Electron Devices.

[6]  S. Dasgupta,et al.  Low-power and robust 6T SRAM cell using symmetric dual-k spacer FinFETs , 2014, 2014 29th International Conference on Microelectronics Proceedings - MIEL 2014.

[7]  Seung-Hwan Kim,et al.  Design Optimization and Performance Projections of Double-Gate FinFETs With Gate–Source/Drain Underlap for SRAM Application , 2007, IEEE Transactions on Electron Devices.

[8]  Min-hwa Chi.  Challenges in Manufacturing FinFET at 20 nm node and beyond , 2012 .

[9]  Brajesh Kumar Kaushik,et al.  Optimization of Underlap FinFETs and Its SRAM Performance Projections Using High-k Spacers , 2013, VDAT.

[10]  V. Trivedi,et al.  Nanoscale FinFETs with gate-source/drain underlap , 2005, IEEE Transactions on Electron Devices.

[11]  Brajesh Kumar Kaushik,et al.  High-Performance and Robust SRAM Cell Based on Asymmetric Dual-$k$ Spacer FinFETs , 2013, IEEE Transactions on Electron Devices.

[12]  T. Hiramoto,et al.  Impact of DIBL variability on SRAM static noise margin analyzed by DMA SRAM TEG , 2010, 2010 International Electron Devices Meeting.

[13]  Brajesh Kumar Kaushik,et al.  Investigation of Symmetric Dual- \(k\) Spacer Trigate FinFETs From Delay Perspective , 2014, IEEE Transactions on Electron Devices.

[14]  K. Endo,et al.  Grain-Orientation Induced Quantum Confinement Variation in FinFETs and Multi-Gate Ultra-Thin Body CMOS Devices and Implications for Digital Design , 2011, IEEE Transactions on Electron Devices.

[15]  C. Hu,et al.  Denser and More Stable SRAM Using FinFETs With Multiple Fin Heights , 2012, IEEE Transactions on Electron Devices.

[16]  Hui Zhao,et al.  Analysis of the Effects of Fringing Electric Field on FinFET Device Performance and Structural Optimization Using 3-D Simulation , 2008, IEEE Transactions on Electron Devices.