A High Performance FPGA-Based Architecture for the Future Video Coding Adaptive Multiple Core Transform

Future video coding (FVC) will be the next generation video coding standard. Yet in the first stages of the standardization process, it is expected to replace high efficiency video coding beyond 2020. One of the enhancements in discussion is the adaptive multiple core transform, which uses five different types of 2-D discrete sine/cosine transforms (DCT-II, DCT-V, DCT-VIII, DST-I, and DST-VII) and up to <inline-formula> <tex-math notation="LaTeX">${64 \times 64}$ </tex-math></inline-formula> transform unit sizes. This schema, increases the computational complexity of both, encoder and decoder. In this paper, a deeply pipelined high performance architecture to implement the five transforms for <inline-formula> <tex-math notation="LaTeX">${4 \times 4}$ </tex-math></inline-formula>, <inline-formula> <tex-math notation="LaTeX">${8 \times 8}$ </tex-math></inline-formula>, <inline-formula> <tex-math notation="LaTeX">${16 \times 16}$ </tex-math></inline-formula>, and <inline-formula> <tex-math notation="LaTeX">${32 \times 32}$ </tex-math></inline-formula> sizes is proposed. The design has been described in VHDL and it has been synthesized for different Field-programmable gate array chips, being able to process up 182 fps<inline-formula> <tex-math notation="LaTeX">${@} 3840\times2160$ </tex-math></inline-formula> for <inline-formula> <tex-math notation="LaTeX">${4 \times 4}$ </tex-math></inline-formula> transform sizes. Up the best of our knowledge, this is the first implementation of an architecture for the FVC Adaptive Multiple Core Transform supporting <inline-formula> <tex-math notation="LaTeX">${4 \times 4}$ </tex-math></inline-formula>, <inline-formula> <tex-math notation="LaTeX">${8 \times 8}$ </tex-math></inline-formula>, <inline-formula> <tex-math notation="LaTeX">${16 \times 16}$ </tex-math></inline-formula>, and <inline-formula> <tex-math notation="LaTeX">${32 \times 32}$ </tex-math></inline-formula> sizes.